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a way consistent with the position of the register field in the instruction. In Intel encoding parlance, the G register is in bits 5,4,3 and the E register is bits 2,1,0, and so we adopt this scheme consistently. Considering how much confusion this has caused me in this recent bout of SSE hacking, consistent renaming can only be a good thing. It makes it a lot easier to figure out if parts of the SSE handling machinery are correct, or not. git-svn-id: svn://svn.valgrind.org/valgrind/trunk@1698