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https://github.com/Zenithsiz/ftmemsim-valgrind.git
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3a5719678f
The number of sets, ie. number of cache lines divided by associativity,
and the cache line size still have to be powers of two.
This change is needed for default cache parameters used on some Intel
Core 2 and Atom processors.
Includes cachegrind manual update and explicit tests with 24KB D1/3MB L2
Reverts addition of 6MB warning to {cachegrind,callgrind}/tests/filter_stderr
Backporting to VALGRIND_3_4_BRANCH needs r8912
git-svn-id: svn://svn.valgrind.org/valgrind/trunk@9080
199 lines
11 KiB
C
199 lines
11 KiB
C
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/*--------------------------------------------------------------------*/
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/*--- Cache simulation cg_sim.c ---*/
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/*--------------------------------------------------------------------*/
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/*
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This file is part of Cachegrind, a Valgrind tool for cache
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profiling programs.
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Copyright (C) 2002-2008 Nicholas Nethercote
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njn@valgrind.org
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This program is free software; you can redistribute it and/or
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modify it under the terms of the GNU General Public License as
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published by the Free Software Foundation; either version 2 of the
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License, or (at your option) any later version.
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This program is distributed in the hope that it will be useful, but
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WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with this program; if not, write to the Free Software
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Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA
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02111-1307, USA.
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The GNU General Public License is contained in the file COPYING.
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*/
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/* Notes:
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- simulates a write-allocate cache
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- (block --> set) hash function uses simple bit selection
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- handling of references straddling two cache blocks:
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- counts as only one cache access (not two)
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- both blocks hit --> one hit
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- one block hits, the other misses --> one miss
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- both blocks miss --> one miss (not two)
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*/
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typedef struct {
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Int size; /* bytes */
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Int assoc;
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Int line_size; /* bytes */
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Int sets;
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Int sets_min_1;
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Int line_size_bits;
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Int tag_shift;
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Char desc_line[128];
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UWord* tags;
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} cache_t2;
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/* By this point, the size/assoc/line_size has been checked. */
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static void cachesim_initcache(cache_t config, cache_t2* c)
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{
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Int i;
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c->size = config.size;
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c->assoc = config.assoc;
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c->line_size = config.line_size;
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c->sets = (c->size / c->line_size) / c->assoc;
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c->sets_min_1 = c->sets - 1;
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c->line_size_bits = VG_(log2)(c->line_size);
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c->tag_shift = c->line_size_bits + VG_(log2)(c->sets);
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if (c->assoc == 1) {
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VG_(sprintf)(c->desc_line, "%d B, %d B, direct-mapped",
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c->size, c->line_size);
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} else {
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VG_(sprintf)(c->desc_line, "%d B, %d B, %d-way associative",
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c->size, c->line_size, c->assoc);
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}
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c->tags = VG_(malloc)("cg.sim.ci.1",
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sizeof(UWord) * c->sets * c->assoc);
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for (i = 0; i < c->sets * c->assoc; i++)
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c->tags[i] = 0;
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}
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/* This is done as a macro rather than by passing in the cache_t2 as an
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* arg because it slows things down by a small amount (3-5%) due to all
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* that extra indirection. */
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#define CACHESIM(L, MISS_TREATMENT) \
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/* The cache and associated bits and pieces. */ \
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static cache_t2 L; \
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\
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static void cachesim_##L##_initcache(cache_t config) \
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{ \
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cachesim_initcache(config, &L); \
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} \
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\
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/* This attribute forces GCC to inline this function, even though it's */ \
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/* bigger than its usual limit. Inlining gains around 5--10% speedup. */ \
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__attribute__((always_inline)) \
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static __inline__ \
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void cachesim_##L##_doref(Addr a, UChar size, ULong* m1, ULong *m2) \
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{ \
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UInt set1 = ( a >> L.line_size_bits) & (L.sets_min_1); \
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UInt set2 = ((a+size-1) >> L.line_size_bits) & (L.sets_min_1); \
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UWord tag = a >> L.tag_shift; \
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UWord tag2; \
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Int i, j; \
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Bool is_miss = False; \
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UWord* set; \
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\
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/* First case: word entirely within line. */ \
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if (set1 == set2) { \
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\
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set = &(L.tags[set1 * L.assoc]); \
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\
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/* This loop is unrolled for just the first case, which is the most */\
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/* common. We can't unroll any further because it would screw up */\
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/* if we have a direct-mapped (1-way) cache. */\
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if (tag == set[0]) { \
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return; \
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} \
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/* If the tag is one other than the MRU, move it into the MRU spot */\
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/* and shuffle the rest down. */\
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for (i = 1; i < L.assoc; i++) { \
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if (tag == set[i]) { \
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for (j = i; j > 0; j--) { \
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set[j] = set[j - 1]; \
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} \
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set[0] = tag; \
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return; \
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} \
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} \
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\
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/* A miss; install this tag as MRU, shuffle rest down. */ \
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for (j = L.assoc - 1; j > 0; j--) { \
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set[j] = set[j - 1]; \
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} \
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set[0] = tag; \
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MISS_TREATMENT; \
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return; \
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\
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/* Second case: word straddles two lines. */ \
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/* Nb: this is a fast way of doing ((set1+1) % L.sets) */ \
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} else if (((set1 + 1) & (L.sets-1)) == set2) { \
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set = &(L.tags[set1 * L.assoc]); \
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if (tag == set[0]) { \
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goto block2; \
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} \
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for (i = 1; i < L.assoc; i++) { \
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if (tag == set[i]) { \
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for (j = i; j > 0; j--) { \
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set[j] = set[j - 1]; \
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} \
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set[0] = tag; \
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goto block2; \
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} \
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} \
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for (j = L.assoc - 1; j > 0; j--) { \
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set[j] = set[j - 1]; \
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} \
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set[0] = tag; \
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is_miss = True; \
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block2: \
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set = &(L.tags[set2 * L.assoc]); \
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tag2 = (a+size-1) >> L.tag_shift; \
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if (tag2 == set[0]) { \
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goto miss_treatment; \
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} \
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for (i = 1; i < L.assoc; i++) { \
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if (tag2 == set[i]) { \
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for (j = i; j > 0; j--) { \
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set[j] = set[j - 1]; \
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} \
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set[0] = tag2; \
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goto miss_treatment; \
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} \
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} \
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for (j = L.assoc - 1; j > 0; j--) { \
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set[j] = set[j - 1]; \
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} \
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set[0] = tag2; \
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is_miss = True; \
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miss_treatment: \
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if (is_miss) { MISS_TREATMENT; } \
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\
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} else { \
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VG_(printf)("addr: %lx size: %u sets: %d %d", a, size, set1, set2);\
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VG_(tool_panic)("item straddles more than two cache sets"); \
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} \
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return; \
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}
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CACHESIM(L2, (*m2)++ );
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CACHESIM(I1, { (*m1)++; cachesim_L2_doref(a, size, m1, m2); } );
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CACHESIM(D1, { (*m1)++; cachesim_L2_doref(a, size, m1, m2); } );
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/*--------------------------------------------------------------------*/
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/*--- end cg_sim.c ---*/
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/*--------------------------------------------------------------------*/
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