mirror of
https://github.com/Zenithsiz/ftmemsim-valgrind.git
synced 2026-02-05 19:13:46 +00:00
1818ed0e51
Discovered sometimes a SLINE stabs entry is the last one (which broke an
assertion). In such a case, we must guess the line's instruction address
range -- I've guessed 4, arbitrarily.
vg_cachegen.in, vg_cachesim_{I1,D1,L2}.c:
Discovered a bad bug in the cache simulation: when determining if a
references straddles two memory blocks, to find the end of the range I was
adding 'size' to the base address, rather than 'size - 1'. This was
causing way too many straddled references, which would inflate the miss
counts.
vg_cachesim.c:
Minor stuff
git-svn-id: svn://svn.valgrind.org/valgrind/trunk@176
94 lines
2.2 KiB
C
94 lines
2.2 KiB
C
/* D1 cache simulator, generated by vg_cachegen.
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* total size = 65536 bytes
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* line size = 64 bytes
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* associativity = 2-way associative
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*
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* This file should be #include-d into vg_cachesim.c
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*/
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static char D1_desc_line[] =
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"desc: D1 cache: 65536 B, 64 B, 2-way associative\n";
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static UInt D1_tags[512][2];
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static void cachesim_D1_initcache(void)
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{
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UInt set, way;
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for (set = 0; set < 512; set++)
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for (way = 0; way < 2; way++)
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D1_tags[set][way] = 0;
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}
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static __inline__
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void cachesim_D1_doref(Addr a, UChar size, ULong* m1, ULong *m2)
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{
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register UInt set1 = ( a >> 6) & (512-1);
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register UInt set2 = ((a + size - 1) >> 6) & (512-1);
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register UInt tag = a >> (6 + 9);
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if (set1 == set2) {
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if (tag == D1_tags[set1][0]) {
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return;
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}
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else if (tag == D1_tags[set1][1]) {
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D1_tags[set1][1] = D1_tags[set1][0];
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D1_tags[set1][0] = tag;
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return;
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}
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else {
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/* A miss */
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D1_tags[set1][1] = D1_tags[set1][0];
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D1_tags[set1][0] = tag;
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(*m1)++;
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cachesim_L2_doref(a, size, m2);
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}
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} else if ((set1 + 1) % 512 == set2) {
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Bool is_D1_miss = False;
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/* Block one */
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if (tag == D1_tags[set1][0]) {
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}
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else if (tag == D1_tags[set1][1]) {
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D1_tags[set1][1] = D1_tags[set1][0];
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D1_tags[set1][0] = tag;
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}
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else {
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/* A miss */
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D1_tags[set1][1] = D1_tags[set1][0];
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D1_tags[set1][0] = tag;
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is_D1_miss = True;
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}
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/* Block two */
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if (tag == D1_tags[set2][0]) {
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}
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else if (tag == D1_tags[set2][1]) {
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D1_tags[set2][1] = D1_tags[set2][0];
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D1_tags[set2][0] = tag;
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}
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else {
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/* A miss */
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D1_tags[set2][1] = D1_tags[set2][0];
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D1_tags[set2][0] = tag;
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is_D1_miss = True;
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}
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/* Miss treatment */
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if (is_D1_miss) {
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(*m1)++;
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cachesim_L2_doref(a, size, m2);
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}
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} else {
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VG_(printf)("\nERROR: Data item 0x%x of size %u bytes is in two non-adjacent\n", a, size);
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VG_(printf)("sets %d and %d.\n", set1, set2);
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VG_(panic)("D1 cache set mismatch");
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}
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}
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