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https://github.com/Zenithsiz/ftmemsim-valgrind.git
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91d5bb2015
Change the existing tests to print the value of the FCSR register after the mips fpu instruction is executed. Add tests that are testing the value of FCSR register. git-svn-id: svn://svn.valgrind.org/valgrind/trunk@13560
355 lines
13 KiB
C
355 lines
13 KiB
C
#include "const.h"
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typedef enum {
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ABSS=0, ABSD, ADDS, ADDD,
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DIVS, DIVD, MULS, MULD,
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NEGS, NEGD, SQRTS, SQRTD,
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SUBS, SUBD, RECIPS, RECIPD,
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RSQRTS, RSQRTD, MSUBS, MSUBD,
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MADDS, MADDD, NMADDS, NMADDD,
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NMSUBS, NMSUBD
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} flt_art_op_t;
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typedef enum {
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CEILWS=0, CEILWD, FLOORWS, FLOORWD,
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ROUNDWS, ROUNDWD, TRUNCWS, TRUNCWD,
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CEILLS, CEILLD, FLOORLS, FLOORLD,
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ROUNDLS, ROUNDLD, TRUNCLS, TRUNCLD
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} flt_dir_op_t;
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typedef enum {
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CVTDS, CVTDW, CVTSD, CVTSW,
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CVTWS, CVTWD, CVTDL, CVTLS,
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CVTLD, CVTSL,
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} flt_round_op_t;
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const char *flt_art_op_names[] = {
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"abs.s", "abs.d", "add.s", "add.d",
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"div.s", "div.d", "mul.s", "mul.d",
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"neg.s", "neg.d", "sqrt.s", "sqrt.d",
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"sub.s", "sub.d", "recip.s", "recip.d",
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"rsqrt.s", "rsqrt.d", "msub.s", "msub.d",
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"madd.s", "madd.d", "nmadd.s", "nmadd.d",
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"nmsub.s", "nmsub.d"
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};
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const char *flt_dir_op_names[] = {
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"ceil.w.s", "ceil.w.d",
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"floor.w.s", "floor.w.d",
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"round.w.s", "round.w.d",
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"trunc.w.s", "trunc.w.d",
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"ceil.l.s", "ceil.l.d",
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"floor.l.s", "floor.l.d",
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"round.l.s", "round.l.d",
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"trunc.l.s", "trunc.l.d"
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};
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const char *flt_round_op_names[] = {
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"cvt.d.s", "cvt.d.w",
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"cvt.s.d", "cvt.s.w",
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"cvt.w.s", "cvt.w.d",
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"cvt.d.l", "cvt.l.s",
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"cvt.l.d", "cvt.s.l",
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};
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#define UNOPdd(op) \
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fd_d = 0; \
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__asm__ __volatile__( \
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op" %1, %2" "\n\t" \
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"cfc1 %0, $31" "\n\t" \
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: "=r" (fcsr), "=f"(fd_d) \
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: "f"(fs_d[i]) \
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);
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#define UNOPff(op) \
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fd_f = 0; \
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__asm__ __volatile__( \
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op" %1, %2" "\n\t" \
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"cfc1 %0, $31" "\n\t" \
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: "=r" (fcsr), "=f"(fd_f) \
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: "f"(fs_f[i]) \
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);
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#define UNOPfd(op) \
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fd_d = 0; \
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__asm__ __volatile__( \
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op" %1, %2" "\n\t" \
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"cfc1 %0, $31" "\n\t" \
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: "=r" (fcsr), "=f"(fd_d) \
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: "f"(fs_f[i]) \
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);
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#define UNOPdf(op) \
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fd_f = 0; \
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__asm__ __volatile__( \
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op" %1, %2" "\n\t" \
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"cfc1 %0, $31" "\n\t" \
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: "=r" (fcsr), "=f"(fd_f) \
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: "f"(fs_d[i]) \
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);
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#define UNOPfw(op) \
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fd_w = 0; \
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__asm__ __volatile__( \
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op" $f0, %2" "\n\t" \
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"mfc1 %1, $f0" "\n\t" \
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"cfc1 %0, $31" "\n\t" \
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: "=r" (fcsr), "=r"(fd_w) \
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: "f"(fs_f[i]) \
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: "$f0" \
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);
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#define UNOPdw(op) \
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fd_w = 0; \
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__asm__ __volatile__( \
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op" $f0, %2" "\n\t" \
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"mfc1 %1, $f0" "\n\t" \
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"cfc1 %0, $31" "\n\t" \
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: "=r" (fcsr), "=r"(fd_w) \
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: "f"(fs_d[i]) \
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: "$f0" \
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);
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#define UNOPwd(op) \
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fd_d = 0; \
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__asm__ __volatile__( \
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"mtc1 %2, $f0" "\n\t" \
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op" %1, $f0" "\n\t" \
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"cfc1 %0, $31" "\n\t" \
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: "=r" (fcsr), "=f"(fd_d) \
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: "r"(fs_w[i]) \
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: "$f0" \
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);
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#define UNOPwf(op) \
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fd_f = 0; \
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__asm__ __volatile__( \
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"mtc1 %2, $f0" "\n\t" \
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op" %1, $f0" "\n\t" \
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"cfc1 %0, $31" "\n\t" \
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: "=r" (fcsr), "=f"(fd_f) \
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: "r"(fs_w[i]) \
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: "$f0" \
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);
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#define UNOPld(op) \
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fd_d = 0; \
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__asm__ __volatile__( \
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"dmtc1 %2, $f0" "\n\t" \
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op" %1, $f0" "\n\t" \
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"cfc1 %0, $31" "\n\t" \
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: "=r" (fcsr), "=f"(fd_d) \
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: "r"(fs_l[i]) \
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: "$f0" \
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);
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#define UNOPdl(op) \
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fd_l = 0; \
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__asm__ __volatile__( \
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op" $f0, %2" "\n\t" \
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"dmfc1 %1, $f0" "\n\t" \
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"cfc1 %0, $31" "\n\t" \
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: "=r" (fcsr), "=r"(fd_l) \
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: "f"(fs_d[i]) \
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: "$f0" \
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);
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#define UNOPls(op) \
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fd_f = 0; \
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__asm__ __volatile__( \
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"dmtc1 %2, $f0" "\n\t" \
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op" %1, $f0" "\n\t" \
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"cfc1 %0, $31" "\n\t" \
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: "=r" (fcsr), "=f"(fd_f) \
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: "r"(fs_l[i]) \
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: "$f0" \
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);
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#define UNOPsl(op) \
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fd_l = 0; \
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__asm__ __volatile__( \
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op" $f0, %2" "\n\t" \
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"dmfc1 %1, $f0" "\n\t" \
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"cfc1 %0, $31" "\n\t" \
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: "=r" (fcsr), "=r"(fd_l) \
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: "f"(fs_f[i]) \
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: "$f0" \
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);
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#define BINOPf(op) \
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fd_f = 0; \
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__asm__ __volatile__( \
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op" %1, %2, %3" "\n\t" \
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"cfc1 %0, $31" "\n\t" \
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: "=r" (fcsr), "=f" (fd_f) \
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: "f" (fs_f[i]), "f" (ft_f[i]) \
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);
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#define BINOPd(op) \
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fd_d = 0; \
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__asm__ __volatile__( \
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op" %1, %2, %3" "\n\t" \
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"cfc1 %0, $31" "\n\t" \
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: "=r" (fcsr), "=f"(fd_d) \
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: "f" (fs_d[i]), "f" (ft_d[i]) \
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);
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#define TRIOPf(op) \
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fd_f = 0; \
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__asm__ __volatile__( \
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op" %1, %2, %3, %4" "\n\t" \
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"cfc1 %0, $31" "\n\t" \
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: "=r" (fcsr), "=f" (fd_f) \
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: "f" (fr_f[i]), "f" (fs_f[i]) , "f" (ft_f[i]) \
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);
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#define TRIOPd(op) \
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fd_d = 0; \
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__asm__ __volatile__( \
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op" %1, %2, %3, %4" "\n\t" \
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"cfc1 %0, $31" "\n\t" \
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: "=r" (fcsr), "=f"(fd_d) \
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: "f" (fr_d[i]), "f" (fs_d[i]) , "f" (ft_d[i]) \
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);
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/* Conditional macros.*/
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#define TESTINST1s(instruction, RDval) \
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{ \
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float outf = 0; \
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__asm__ __volatile__( \
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".set noreorder" "\n\t" \
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"mov.s $f1, %1" "\n\t" \
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"mov.s $f2, %2" "\n\t" \
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"mtc1 $zero, $f0" "\n\t" \
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"c.eq.s $f1, $f2" "\n\t" \
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instruction" end"instruction"s"#RDval "\n\t" \
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"nop" "\n\t" \
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"add.s $f0, $f0, $f1" "\n\t" \
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"end"instruction"s"#RDval":" "\n\t" \
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"add.s $f0, $f0, $f2" "\n\t" \
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"mov.s %0, $f0" "\n\t" \
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".set reorder" "\n\t" \
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: "=f" (outf) \
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: "f" (fs_f[i]) , "f" (ft_f[i]) \
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: "$f0", "$f1", "$f2" \
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); \
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printf("%s, c.eq.s out=%f, fs=%f, ft=%f\n", \
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instruction, outf, fs_f[i], ft_f[i]); \
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}
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#define TESTINST1d(instruction, RDval) \
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{ \
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double outd = 0; \
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__asm__ __volatile__( \
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".set noreorder" "\n\t" \
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"mov.d $f1, %1" "\n\t" \
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"mov.d $f2, %2" "\n\t" \
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"dmtc1 $zero, $f0" "\n\t" \
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"c.eq.d $f1, $f2" "\n\t" \
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instruction" end"instruction"d"#RDval "\n\t" \
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"nop" "\n\t" \
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"add.d $f0, $f0, $f1" "\n\t" \
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"end"instruction"d"#RDval":" "\n\t" \
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"add.d $f0, $f0, $f2" "\n\t" \
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"mov.d %0, $f0" "\n\t" \
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".set reorder" "\n\t" \
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: "=f" (outd) \
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: "f" (fs_d[i]) , "f" (ft_d[i]) \
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: "$f0", "$f1", "$f2" \
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); \
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printf("%s, c.eq.d out=%f, fs=%f, ft=%f\n", \
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instruction, outd, fs_d[i], ft_d[i]); \
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}
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#define TESTINST2s(instruction, RDval) \
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{ \
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float outf = 0; \
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__asm__ __volatile__( \
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".set noreorder" "\n\t" \
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"mov.s $f1, %1" "\n\t" \
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"mov.s $f2, %2" "\n\t" \
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"mtc1 $zero, $f0" "\n\t" \
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"c.eq.s $f1, $f2" "\n\t" \
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instruction" end"instruction"s"#RDval "\n\t" \
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"add.s $f0, $f0, $f1" "\n\t" \
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"end"instruction"s"#RDval":" "\n\t" \
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"add.s $f0, $f0, $f2" "\n\t" \
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"mov.s %0, $f0" "\n\t" \
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".set reorder" "\n\t" \
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: "=f" (outf) \
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: "f" (fs_f[i]) , "f" (ft_f[i]) \
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: "$f0", "$f1", "$f2" \
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); \
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printf("%s, c.eq.s out=%f, fs=%f, ft=%f\n", \
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instruction, outf, fs_f[i], ft_f[i]); \
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}
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#define TESTINST2d(instruction, RDval) \
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{ \
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double outd = 0; \
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__asm__ __volatile__( \
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".set noreorder" "\n\t" \
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"mov.d $f1, %1" "\n\t" \
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"mov.d $f2, %2" "\n\t" \
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"dmtc1 $zero, $f0" "\n\t" \
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"c.eq.d $f1, $f2" "\n\t" \
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instruction" end"instruction"d"#RDval "\n\t" \
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"add.d $f0, $f0, $f1" "\n\t" \
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"end"instruction"d"#RDval":" "\n\t" \
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"add.d $f0, $f0, $f2" "\n\t" \
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"mov.d %0, $f0" "\n\t" \
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".set reorder" "\n\t" \
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: "=f" (outd) \
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: "f" (fs_d[i]) , "f" (ft_d[i]) \
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: "$f0", "$f1", "$f2" \
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); \
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printf("%s, c.eq.d out=%f, fs=%f, ft=%f\n", \
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instruction, outd, fs_d[i], ft_d[i]); \
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}
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#define TESTINST_CONDs(instruction, RDval) \
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{ \
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float outf = 0; \
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__asm__ __volatile__( \
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".set noreorder" "\n\t" \
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"mov.s $f1, %1" "\n\t" \
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"mov.s $f2, %2" "\n\t" \
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"mov.s $f0, %1" "\n\t" \
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instruction" $f1, $f2" "\n\t" \
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"bc1f end"instruction"s"#RDval "\n\t" \
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"nop" "\n\t" \
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"add.s $f0, $f0, $f2" "\n\t" \
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"end"instruction"s"#RDval":" "\n\t" \
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"mov.s %0, $f0" "\n\t" \
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".set reorder" "\n\t" \
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: "=f" (outf) \
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: "f" (fs_f[i]) , "f" (ft_f[i]) \
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: "$f0", "$f1", "$f2" \
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); \
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printf("%s, bc1f out=%f, fs=%f, ft=%f\n", \
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instruction, outf, fs_f[i], ft_f[i]); \
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}
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#define TESTINST_CONDd(instruction, RDval) \
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{ \
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double outd = 0; \
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__asm__ __volatile__( \
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".set noreorder" "\n\t" \
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"mov.d $f1, %1" "\n\t" \
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"mov.d $f2, %2" "\n\t" \
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"mov.d $f0, %1" "\n\t" \
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instruction" $f1, $f2" "\n\t" \
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"bc1f end"instruction"d"#RDval "\n\t" \
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"nop" "\n\t" \
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"add.d $f0, $f0, $f2" "\n\t" \
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"end"instruction"d"#RDval":" "\n\t" \
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"mov.d %0, $f0" "\n\t" \
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".set reorder" "\n\t" \
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: "=f" (outd) \
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: "f" (fs_d[i]) , "f" (ft_d[i]) \
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: "$f0", "$f1", "$f2" \
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); \
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printf("%s, bc1f out=%f, fs=%f, ft=%f\n", \
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instruction, outd, fs_d[i], ft_d[i]); \
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}
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