mirror of
https://github.com/Zenithsiz/ftmemsim-valgrind.git
synced 2026-02-04 02:18:37 +00:00
1818ed0e51
Discovered sometimes a SLINE stabs entry is the last one (which broke an
assertion). In such a case, we must guess the line's instruction address
range -- I've guessed 4, arbitrarily.
vg_cachegen.in, vg_cachesim_{I1,D1,L2}.c:
Discovered a bad bug in the cache simulation: when determining if a
references straddles two memory blocks, to find the end of the range I was
adding 'size' to the base address, rather than 'size - 1'. This was
causing way too many straddled references, which would inflate the miss
counts.
vg_cachesim.c:
Minor stuff
git-svn-id: svn://svn.valgrind.org/valgrind/trunk@176
301 lines
8.8 KiB
Perl
Executable File
301 lines
8.8 KiB
Perl
Executable File
#! /usr/bin/perl -w
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##--------------------------------------------------------------------##
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##--- The cache simulator generator ---##
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##--- vg_cachegen ---##
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##--------------------------------------------------------------------##
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# This file is part of Valgrind, an x86 protected-mode emulator
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# designed for debugging and profiling binaries on x86-Unixes.
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#
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# Copyright (C) 2000-2002 Julian Seward
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# jseward@acm.org
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# Julian_Seward@muraroa.demon.co.uk
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#
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# This program is free software; you can redistribute it and/or
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# modify it under the terms of the GNU General Public License as
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# published by the Free Software Foundation; either version 2 of the
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# License, or (at your option) any later version.
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#
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# This program is distributed in the hope that it will be useful, but
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# WITHOUT ANY WARRANTY; without even the implied warranty of
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# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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# General Public License for more details.
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#
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# You should have received a copy of the GNU General Public License
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# along with this program; if not, write to the Free Software
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# Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA
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# 02111-1307, USA.
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#
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# The GNU General Public License is contained in the file LICENSE.
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#----------------------------------------------------------------------------
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# Cache simulator generator, creates files vg_cachesim_{I1,D1,L2}.c to be
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# #included in vg_cachesim.c.
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#
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# Notes:
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# - simulates a write-allocate cache
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# - (block --> set) hash function uses simple bit selection
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# - handling references straddling two cache blocks:
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# - counts as only one cache access (not two)
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# - both blocks hit --> one hit
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# - one block hits, the other misses --> one miss
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# - both blocks miss --> one miss (not two)
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use strict;
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#----------------------------------------------------------------------------
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# Global variables
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#----------------------------------------------------------------------------
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my %log2 =
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( 1 => 0,
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2 => 1,
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4 => 2,
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8 => 3,
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16 => 4,
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32 => 5,
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64 => 6,
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128 => 7,
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256 => 8,
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512 => 9,
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1024 => 10,
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2048 => 11,
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4096 => 12,
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8192 => 13,
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16384 => 14,
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32768 => 15,
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65536 => 16,
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131072 => 17,
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262144 => 18,
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524288 => 19,
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1048576 => 20,
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2097152 => 21,
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4194304 => 22,
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8388608 => 23,
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16777216 => 24,
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33554432 => 25,
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67108864 => 26,
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134217728 => 27,
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268435456 => 28,
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536870912 => 29,
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1073741824 => 30);
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my @valid_types =
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("I1", "D1", "L2");
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my @valid_sizes =
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(1024, 2048, 4096, 8192, 16384, 32768, 65536, 131072, 262144, 524288,
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1048576, 2097152, 4194304, 8388608, 16777216, 67108864, 134217728);
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my @valid_linesizes =
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(8, 16, 32, 64, 128);
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my @valid_ways =
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(1, 2, 4, 8, 256);
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my %valid_types; for my $i (@valid_types) { $valid_types{$i} = 1; }
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my %valid_sizes; for my $i (@valid_sizes) { $valid_sizes{$i} = 1; }
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my %valid_linesizes; for my $i (@valid_linesizes) { $valid_linesizes{$i} = 1; }
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my %valid_ways; for my $i (@valid_ways) { $valid_ways{$i} = 1; }
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my ($L, $size, $line_size, $n_ways);
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my @caches;
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#----------------------------------------------------------------------------
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# Argument and option handling
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#----------------------------------------------------------------------------
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sub process_cmd_line ()
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{
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#----
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my $usage = <<END
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usage: cachegen [options]
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options are:
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--I1=size,line_size,number_of_ways
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--D1=size,line_size,number_of_ways
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--L2=size,line_size,number_of_ways
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where
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size is one of @valid_sizes
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line_size is one of @valid_linesizes
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number_of_ways is one of @valid_ways
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Valgrind is Copyright (C) 2000-2002 Julian Seward
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and licensed under the GNU General Public License, version 2.
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Bug reports, feedback, admiration, abuse, etc, to: jseward\@acm.org.
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END
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;
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#----
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(@ARGV > 0) or die($usage);
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for my $arg (@ARGV) {
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if ($arg =~ /--(I1|D1|L2)=(\d+),(\d+),(\d+)/) {
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my ($L, $size, $line_size, $n_ways) = ($1, $2, $3, $4);
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(defined $valid_sizes{$size} &&
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defined $valid_linesizes{$line_size} &&
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defined $valid_ways{$n_ways}) or die($usage);
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# Remember cache type too, and save
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push(@caches, [ $L, $size, $line_size, $n_ways ]);
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}
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else { # -h and --help fall under this case
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die($usage);
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}
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}
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}
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#----------------------------------------------------------------------------
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# Printing machinery (I)
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#----------------------------------------------------------------------------
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sub shiftSequence ($$$)
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{
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my $s = "";
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my ($i, $n, $L) = @_;
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while ($i > 0) {
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$s .= " ${L}_tags[set$n][$i] = ";
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$i--;
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$s .= "${L}_tags[set$n][$i];\n"
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}
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return $s;
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}
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sub trySet ($$$$$)
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{
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my $s = "";
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my ($k, $n, $L, $hit_ending, $miss_ending) = @_;
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for (my $i = 0; $i < $k; $i++) {
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$s .= " "
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. (0 == $i ? "if" : "else if")
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. " (tag == ${L}_tags[set$n][$i]) {\n"
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. shiftSequence($i, $n, $L)
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. (0 == $i ? "" : " ${L}_tags[set$n][0] = tag;\n")
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. ("" eq $hit_ending ? "" : " $hit_ending\n")
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. " }\n";
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}
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$s .= " else {\n"
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. " /* A miss */\n"
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. shiftSequence($k - 1, $n, $L) # not if exclusive
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. " ${L}_tags[set$n][0] = tag;\n" # not if exclusive
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. "\n"
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. " $miss_ending\n"
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. " }\n";
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return $s;
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}
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sub print_cache_simulator (@)
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{
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my ($L, $size, $line_size, $n_ways) = @_;
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my $n_lines = $size / $line_size;
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my $n_sets = $n_lines / $n_ways;
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my $n_line_bits = $log2{$line_size};
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my $n_set_bits = $log2{$n_sets};
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my $assoc = (1 == $n_ways ? "direct-mapped" : "$n_ways-way associative");
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my $L1_args = "Addr a, UChar size, ULong* m1, ULong *m2";
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my $L2_args = "Addr a, UChar size, ULong *m2";
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my $L_args = ($L ne "L2" ? $L1_args : $L2_args);
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#----
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my $comments_cache_init_desc_and_doref_start = <<END
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/* $L cache simulator, generated by vg_cachegen.
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* total size = $size bytes
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* line size = $line_size bytes
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* associativity = $assoc
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*
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* This file should be #include-d into vg_cachesim.c
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*/
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static char ${L}_desc_line[] =
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"desc: ${L} cache: $size B, $line_size B, $assoc\\n";
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static UInt ${L}_tags[$n_sets][$n_ways];
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static void cachesim_${L}_initcache(void)
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{
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UInt set, way;
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for (set = 0; set < $n_sets; set++)
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for (way = 0; way < $n_ways; way++)
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${L}_tags[set][way] = 0;
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}
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static __inline__
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void cachesim_${L}_doref($L_args)
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{
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register UInt set1 = ( a >> $n_line_bits) & ($n_sets-1);
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register UInt set2 = ((a + size - 1) >> $n_line_bits) & ($n_sets-1);
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register UInt tag = a >> ($n_line_bits + $n_set_bits);
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if (set1 == set2) {
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END
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;
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#----
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my $doref_middle = <<END
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} else if ((set1 + 1) % $n_sets == set2) {
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Bool is_${L}_miss = False;
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END
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;
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#----
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my $L1_miss_treatment = "(*m1)++;\n" .
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" cachesim_L2_doref(a, size, m2);";
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my $L2_miss_treatment = "(*m2)++;";
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my $L_miss_treatment =
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( $L ne "L2" ? $L1_miss_treatment : $L2_miss_treatment );
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my $straddle_case_miss_treatment = <<END
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/* Miss treatment */
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if (is_${L}_miss) {
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$L_miss_treatment
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}
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END
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;
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#----
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my $doref_end = <<END
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} else {
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VG_(printf)("\\nERROR: Data item 0x%x of size %u bytes is in two non-adjacent\\n", a, size);
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VG_(printf)("sets %d and %d.\\n", set1, set2);
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VG_(panic)("$L cache set mismatch");
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}
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}
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END
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;
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#----
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my $outfile = "vg_cachesim_${L}.c";
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open(OUTFILE, "> $outfile") or die("Couldn't open $outfile for writing\n");
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print(OUTFILE $comments_cache_init_desc_and_doref_start);
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print(OUTFILE trySet($n_ways, 1, $L, "return;", $L_miss_treatment));
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print(OUTFILE $doref_middle);
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print(OUTFILE " /* Block one */\n");
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print(OUTFILE trySet($n_ways, 1, $L, "", "is_${L}_miss = True;"));
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print(OUTFILE "\n");
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print(OUTFILE " /* Block two */\n");
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print(OUTFILE trySet($n_ways, 2, $L, "", "is_${L}_miss = True;"));
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print(OUTFILE "\n");
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print(OUTFILE $straddle_case_miss_treatment);
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print(OUTFILE $doref_end);
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close(OUTFILE);
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}
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#----------------------------------------------------------------------------
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# main()
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#----------------------------------------------------------------------------
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process_cmd_line();
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foreach my $cache (@caches) {
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print_cache_simulator(@$cache);
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}
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