mirror of
https://github.com/Zenithsiz/ftmemsim-valgrind.git
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461cc5c003
Sync VEX/LICENSE.GPL with top-level COPYING file. We used 3 different addresses for writing to the FSF to receive a copy of the GPL. Replace all different variants with an URL <http://www.gnu.org/licenses/>. The following files might still have some slightly different (L)GPL copyright notice because they were derived from other programs: - files under coregrind/m_demangle which come from libiberty: cplus-dem.c, d-demangle.c, demangle.h, rust-demangle.c, safe-ctype.c and safe-ctype.h - coregrind/m_demangle/dyn-string.[hc] derived from GCC. - coregrind/m_demangle/ansidecl.h derived from glibc. - VEX files for FMA detived from glibc: host_generic_maddf.h and host_generic_maddf.c - files under coregrin/m_debuginfo derived from LZO: lzoconf.h, lzodefs.h, minilzo-inl.c and minilzo.h - files under coregrind/m_gdbserver detived from GDB: gdb/signals.h, inferiors.c, regcache.c, regcache.h, regdef.h, remote-utils.c, server.c, server.h, signals.c, target.c, target.h and utils.c Plus the following test files: - none/tests/ppc32/testVMX.c derived from testVMX. - ppc tests derived from QEMU: jm-insns.c, ppc64_helpers.h and test_isa_3_0.c - tests derived from bzip2 (with embedded GPL text in code): hackedbz2.c, origin5-bz2.c, varinfo6.c - tests detived from glibc: str_tester.c, pth_atfork1.c - test detived from GCC libgomp: tc17_sembar.c - performance tests derived from bzip2 or tinycc (with embedded GPL text in code): bz2.c, test_input_for_tinycc.c and tinycc.c
312 lines
10 KiB
ArmAsm
312 lines
10 KiB
ArmAsm
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/*--------------------------------------------------------------------*/
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/*--- The core dispatch loop, for jumping to a code address. ---*/
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/*--- dispatch-x86-linux.S ---*/
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/*--------------------------------------------------------------------*/
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/*
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This file is part of Valgrind, a dynamic binary instrumentation
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framework.
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Copyright (C) 2000-2017 Julian Seward
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jseward@acm.org
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This program is free software; you can redistribute it and/or
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modify it under the terms of the GNU General Public License as
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published by the Free Software Foundation; either version 2 of the
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License, or (at your option) any later version.
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This program is distributed in the hope that it will be useful, but
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WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with this program; if not, see <http://www.gnu.org/licenses/>.
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The GNU General Public License is contained in the file COPYING.
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*/
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#include "pub_core_basics_asm.h"
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#if defined(VGP_x86_linux)
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#include "pub_core_dispatch_asm.h"
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#include "pub_core_transtab_asm.h"
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#include "libvex_guest_offsets.h" /* for OFFSET_x86_EIP */
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/*------------------------------------------------------------*/
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/*--- ---*/
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/*--- The dispatch loop. VG_(disp_run_translations) is ---*/
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/*--- used to run all translations, ---*/
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/*--- including no-redir ones. ---*/
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/*--- ---*/
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/*------------------------------------------------------------*/
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/*----------------------------------------------------*/
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/*--- Entry and preamble (set everything up) ---*/
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/*----------------------------------------------------*/
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/* signature:
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void VG_(disp_run_translations)( UWord* two_words,
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void* guest_state,
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Addr host_addr );
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*/
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.text
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.globl VG_(disp_run_translations)
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.type VG_(disp_run_translations), @function
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VG_(disp_run_translations):
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/* 0(%esp) holds our return address. */
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/* 4(%esp) holds two_words */
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/* 8(%esp) holds guest_state */
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/* 12(%esp) holds host_addr */
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/* The preamble */
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/* Save integer registers, since this is a pseudo-function. */
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pushl %eax
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pushl %ebx
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pushl %ecx
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pushl %edx
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pushl %esi
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pushl %edi
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pushl %ebp
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/* 28+4(%esp) holds two_words */
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/* 28+8(%esp) holds guest_state */
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/* 28+12(%esp) holds host_addr */
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/* Get the host CPU in the state expected by generated code. */
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/* set host FPU control word to the default mode expected
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by VEX-generated code. See comments in libvex.h for
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more info. */
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finit
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pushl $0x027F
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fldcw (%esp)
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addl $4, %esp
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/* set host SSE control word to the default mode expected
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by VEX-generated code. */
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cmpl $0, VG_(machine_x86_have_mxcsr)
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jz L1
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pushl $0x1F80
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ldmxcsr (%esp)
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addl $4, %esp
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L1:
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/* set dir flag to known value */
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cld
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/* Set up the guest state pointer */
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movl 28+8(%esp), %ebp
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/* and jump into the code cache. Chained translations in
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the code cache run, until for whatever reason, they can't
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continue. When that happens, the translation in question
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will jump (or call) to one of the continuation points
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VG_(cp_...) below. */
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jmpl *28+12(%esp)
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/*NOTREACHED*/
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/*----------------------------------------------------*/
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/*--- Postamble and exit. ---*/
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/*----------------------------------------------------*/
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postamble:
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/* At this point, %eax and %edx contain two
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words to be returned to the caller. %eax
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holds a TRC value, and %edx optionally may
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hold another word (for CHAIN_ME exits, the
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address of the place to patch.) */
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/* We're leaving. Check that nobody messed with %mxcsr
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or %fpucw. We can't mess with %eax or %edx here as they
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holds the tentative return value, but any others are OK. */
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#if !defined(ENABLE_INNER)
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/* This check fails for self-hosting, so skip in that case */
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pushl $0
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fstcw (%esp)
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cmpl $0x027F, (%esp)
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popl %esi /* get rid of the word without trashing %eflags */
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jnz invariant_violation
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#endif
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# cmpl $0, VG_(machine_x86_have_mxcsr)
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jz L2
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pushl $0
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stmxcsr (%esp)
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andl $0xFFFFFFC0, (%esp) /* mask out status flags */
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cmpl $0x1F80, (%esp)
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popl %esi
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jnz invariant_violation
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L2: /* otherwise we're OK */
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jmp remove_frame
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invariant_violation:
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movl $VG_TRC_INVARIANT_FAILED, %eax
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movl $0, %edx
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remove_frame:
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/* Stash return values */
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movl 28+4(%esp), %edi /* two_words */
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movl %eax, 0(%edi)
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movl %edx, 4(%edi)
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/* Restore int regs and return. */
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popl %ebp
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popl %edi
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popl %esi
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popl %edx
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popl %ecx
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popl %ebx
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popl %eax
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ret
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/*----------------------------------------------------*/
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/*--- Continuation points ---*/
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/*----------------------------------------------------*/
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/* ------ Chain me to slow entry point ------ */
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.global VG_(disp_cp_chain_me_to_slowEP)
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VG_(disp_cp_chain_me_to_slowEP):
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/* We got called. The return address indicates
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where the patching needs to happen. Collect
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the return address and, exit back to C land,
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handing the caller the pair (Chain_me_S, RA) */
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movl $VG_TRC_CHAIN_ME_TO_SLOW_EP, %eax
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popl %edx
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/* 5 = movl $VG_(disp_chain_me_to_slowEP), %edx;
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2 = call *%edx */
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subl $5+2, %edx
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jmp postamble
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/* ------ Chain me to fast entry point ------ */
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.global VG_(disp_cp_chain_me_to_fastEP)
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VG_(disp_cp_chain_me_to_fastEP):
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/* We got called. The return address indicates
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where the patching needs to happen. Collect
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the return address and, exit back to C land,
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handing the caller the pair (Chain_me_F, RA) */
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movl $VG_TRC_CHAIN_ME_TO_FAST_EP, %eax
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popl %edx
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/* 5 = movl $VG_(disp_chain_me_to_fastEP), %edx;
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2 = call *%edx */
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subl $5+2, %edx
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jmp postamble
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/* ------ Indirect but boring jump ------ */
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.global VG_(disp_cp_xindir)
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VG_(disp_cp_xindir):
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/* Where are we going? */
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movl OFFSET_x86_EIP(%ebp), %eax // "guest"
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/* stats only */
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addl $1, VG_(stats__n_xIndirs_32)
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// LIVE: %ebp (guest state ptr), %eax (guest address to go to).
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// We use 4 temporaries:
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// %esi (to point at the relevant FastCacheSet),
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// %ebx, %ecx and %edx (scratch).
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/* Try a fast lookup in the translation cache. This is pretty much
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a handcoded version of VG_(lookupInFastCache). */
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// Compute %esi = VG_TT_FAST_HASH(guest)
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movl %eax, %esi // guest
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shrl $VG_TT_FAST_BITS, %esi // (guest >> VG_TT_FAST_BITS)
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xorl %eax, %esi // (guest >> VG_TT_FAST_BITS) ^ guest
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andl $VG_TT_FAST_MASK, %esi // setNo
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// Compute %esi = &VG_(tt_fast)[%esi]
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shll $VG_FAST_CACHE_SET_BITS, %esi // setNo * sizeof(FastCacheSet)
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leal VG_(tt_fast)(%esi), %esi // &VG_(tt_fast)[setNo]
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// LIVE: %ebp (guest state ptr), %eax (guest addr), %esi (cache set)
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// try way 0
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cmpl %eax, FCS_g0(%esi) // cmp against .guest0
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jnz 1f
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// hit at way 0
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jmp *FCS_h0(%esi) // goto .host0
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ud2
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1: // try way 1
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cmpl %eax, FCS_g1(%esi) // cmp against .guest1
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jnz 2f
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// hit at way 1; swap upwards
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/* stats only */
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addl $1, VG_(stats__n_xIndir_hits1_32)
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movl FCS_g0(%esi), %ebx // ebx = old .guest0
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movl FCS_h0(%esi), %ecx // ecx = old .host0
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movl FCS_h1(%esi), %edx // edx = old .host1
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movl %eax, FCS_g0(%esi) // new .guest0 = guest
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movl %edx, FCS_h0(%esi) // new .host0 = old .host1
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movl %ebx, FCS_g1(%esi) // new .guest1 = old .guest0
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movl %ecx, FCS_h1(%esi) // new .host1 = old .host0
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jmp *%edx // goto old .host1 a.k.a. new .host0
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ud2
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2: // try way 2
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cmpl %eax, FCS_g2(%esi) // cmp against .guest2
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jnz 3f
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// hit at way 2; swap upwards
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/* stats only */
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addl $1, VG_(stats__n_xIndir_hits2_32)
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movl FCS_g1(%esi), %ebx
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movl FCS_h1(%esi), %ecx
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movl FCS_h2(%esi), %edx
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movl %eax, FCS_g1(%esi)
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movl %edx, FCS_h1(%esi)
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movl %ebx, FCS_g2(%esi)
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movl %ecx, FCS_h2(%esi)
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jmp *%edx
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ud2
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3: // try way 3
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cmpl %eax, FCS_g3(%esi) // cmp against .guest3
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jnz 4f
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// hit at way 3; swap upwards
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/* stats only */
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addl $1, VG_(stats__n_xIndir_hits3_32)
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movl FCS_g2(%esi), %ebx
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movl FCS_h2(%esi), %ecx
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movl FCS_h3(%esi), %edx
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movl %eax, FCS_g2(%esi)
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movl %edx, FCS_h2(%esi)
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movl %ebx, FCS_g3(%esi)
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movl %ecx, FCS_h3(%esi)
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jmp *%edx
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ud2
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4: // fast lookup failed
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/* stats only */
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addl $1, VG_(stats__n_xIndir_misses_32)
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movl $VG_TRC_INNER_FASTMISS, %eax
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movl $0, %edx
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jmp postamble
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/* ------ Assisted jump ------ */
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.global VG_(disp_cp_xassisted)
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VG_(disp_cp_xassisted):
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/* %ebp contains the TRC */
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movl %ebp, %eax
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movl $0, %edx
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jmp postamble
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/* ------ Event check failed ------ */
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.global VG_(disp_cp_evcheck_fail)
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VG_(disp_cp_evcheck_fail):
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movl $VG_TRC_INNER_COUNTERZERO, %eax
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movl $0, %edx
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jmp postamble
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.size VG_(disp_run_translations), .-VG_(disp_run_translations)
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#endif // defined(VGP_x86_linux)
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/* Let the linker know we don't need an executable stack */
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MARK_STACK_NO_EXEC
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/*--------------------------------------------------------------------*/
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/*--- end ---*/
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/*--------------------------------------------------------------------*/
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