mirror of
https://github.com/Zenithsiz/ftmemsim-valgrind.git
synced 2026-02-06 19:54:18 +00:00
23ae8adf30
to include the SSE/SSE2 architectural state. Automagically detect at startup, in vg_startup.S, whether or not this is a SSE-enabled CPU and act accordingly. All subsequent FPU/SSE state transfers between the simulated and real machine are then done either with fsave/frstor (as before) or fxsave/fxrstor (the SSE equivalents). Fragile and fiddly; (1) the SSE state needs to be stored on a 16-byte boundary, and (2) certain bits in the saved MXCSR reg in a state written by fxsave need to be anded out before we can safely restore using fxrstor. It does appear to work. I'd appreciate people trying it out on various CPUs to establish whether the SSE / not-SSE check works right, and/or anything else is broken. Unfortunately makes some programs run significantly slower. I don't know why. Perhaps due to copying around more processor state than there was before (SSE state is 512 bytes, FPU state was only 108). I will look into this. git-svn-id: svn://svn.valgrind.org/valgrind/trunk@1574
559 lines
11 KiB
ArmAsm
559 lines
11 KiB
ArmAsm
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##--------------------------------------------------------------------##
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##--- Support routines for the JITter output. ---##
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##--- vg_helpers.S ---##
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##--------------------------------------------------------------------##
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/*
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This file is part of Valgrind, an extensible x86 protected-mode
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emulator for monitoring program execution on x86-Unixes.
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Copyright (C) 2000-2003 Julian Seward
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jseward@acm.org
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This program is free software; you can redistribute it and/or
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modify it under the terms of the GNU General Public License as
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published by the Free Software Foundation; either version 2 of the
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License, or (at your option) any later version.
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This program is distributed in the hope that it will be useful, but
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WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with this program; if not, write to the Free Software
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Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA
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02111-1307, USA.
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The GNU General Public License is contained in the file COPYING.
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*/
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#include "vg_constants.h"
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/* ------------------ SIMULATED CPU HELPERS ------------------ */
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/* A stubs for a return which we want to catch: a signal return.
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returns and pthread returns. In the latter case, the thread's
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return value is in %EAX, so we pass this as the first argument
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to the request. In both cases we use the user request mechanism.
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You need to to read the definition of VALGRIND_MAGIC_SEQUENCE
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in valgrind.h to make sense of this.
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*/
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.global VG_(signalreturn_bogusRA)
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VG_(signalreturn_bogusRA):
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subl $20, %esp # allocate arg block
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movl %esp, %edx # %edx == &_zzq_args[0]
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movl $VG_USERREQ__SIGNAL_RETURNS, 0(%edx) # request
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movl $0, 4(%edx) # arg1
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movl $0, 8(%edx) # arg2
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movl $0, 12(%edx) # arg3
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movl $0, 16(%edx) # arg4
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movl %edx, %eax
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# and now the magic sequence itself:
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roll $29, %eax
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roll $3, %eax
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rorl $27, %eax
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rorl $5, %eax
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roll $13, %eax
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roll $19, %eax
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# should never get here
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pushl $signalreturn_bogusRA_panic_msg
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call VG_(core_panic)
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.data
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signalreturn_bogusRA_panic_msg:
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.ascii "vg_signalreturn_bogusRA: VG_USERREQ__SIGNAL_RETURNS was missed"
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.byte 0
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.text
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/* ------------------ REAL CPU HELPERS ------------------ */
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/* The rest of this lot run on the real CPU. */
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/* Various helper routines, for instructions which are just too
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darn tedious for the JITter to output code in-line:
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* integer division
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* integer multiplication
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* setting and getting obscure eflags
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* double-length shifts
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All routines use a standard calling convention designed for
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calling from translations, in which the incoming args are
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underneath the return address, the callee saves _all_ registers,
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and the incoming parameters can be modified, to return results.
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*/
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/* Fetch the time-stamp-ctr reg.
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On entry:
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dummy, replaced by %EAX value
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dummy, replaced by %EDX value
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RA <- %esp
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*/
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.global VG_(helper_RDTSC)
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VG_(helper_RDTSC):
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pushl %eax
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pushl %edx
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rdtsc
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movl %edx, 12(%esp)
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movl %eax, 16(%esp)
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popl %edx
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popl %eax
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ret
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/* Do the CPUID instruction.
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On entry:
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dummy, replaced by %EAX value
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dummy, replaced by %EBX value
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dummy, replaced by %ECX value
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dummy, replaced by %EDX value
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RA <- %esp
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As emulating a real CPUID is kinda hard, as it
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has to return different values depending on EAX,
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we just pretend to not support CPUID at all until
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it becomes a problem. This will for sure disable
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all MMX / 3dnow checks so they don't bother us
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with code we don't understand. (Dirk <dirk@kde.org>)
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http://www.sandpile.org/ia32/cpuid.htm
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(Later: we instead pretend to be like Werner's P54C P133, that is
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an original pre-MMX Pentium).
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<werner> cpuid words (0): 0x1 0x756e6547 0x6c65746e 0x49656e69
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<werner> cpuid words (1): 0x52b 0x0 0x0 0x1bf
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*/
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.global VG_(helper_CPUID)
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VG_(helper_CPUID):
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pushl %eax
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pushl %ebx
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pushl %ecx
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pushl %edx
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movl 32(%esp), %eax
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/*
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cpuid
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*/
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/*
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xor %eax,%eax
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xor %ebx,%ebx
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xor %ecx,%ecx
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xor %edx,%edx
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*/
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cmpl $0, %eax
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jz cpuid__0
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movl $0x52b, %eax
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movl $0x0, %ebx
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movl $0x0, %ecx
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movl $0x008001bf, %edx
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jmp cpuid__99
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cpuid__0:
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movl $0x1, %eax
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movl $0x756e6547, %ebx
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movl $0x6c65746e, %ecx
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movl $0x49656e69, %edx
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cpuid__99:
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movl %edx, 20(%esp)
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movl %ecx, 24(%esp)
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movl %ebx, 28(%esp)
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movl %eax, 32(%esp)
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popl %edx
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popl %ecx
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popl %ebx
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popl %eax
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ret
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/* Fetch the FPU status register.
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On entry:
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dummy, replaced by result
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RA <- %esp
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*/
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.global VG_(helper_fstsw_AX)
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VG_(helper_fstsw_AX):
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pushl %eax
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pushl %esi
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movl VGOFF_(m_ssestate), %esi
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pushfl
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cmpb $0, VG_(have_ssestate)
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jz aa1nosse
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fxrstor (%ebp, %esi, 4)
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jmp aa1merge
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aa1nosse:
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frstor (%ebp, %esi, 4)
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aa1merge:
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popfl
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fstsw %ax
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popl %esi
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movw %ax, 8(%esp)
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popl %eax
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ret
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/* Copy %ah into %eflags.
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On entry:
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value of %eax
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RA <- %esp
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*/
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.global VG_(helper_SAHF)
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VG_(helper_SAHF):
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pushl %eax
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movl 8(%esp), %eax
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sahf
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popl %eax
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ret
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/* Do %al = DAS(%al). Note that the passed param has %AL as the least
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significant 8 bits, since it was generated with GETB %AL,
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some-temp. Fortunately %al is the least significant 8 bits of
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%eax anyway, which is why it's safe to work with %eax as a
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whole.
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On entry:
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value of %eax
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RA <- %esp
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*/
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.global VG_(helper_DAS)
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VG_(helper_DAS):
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pushl %eax
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movl 8(%esp), %eax
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das
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movl %eax, 8(%esp)
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popl %eax
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ret
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/* Similarly, do %al = DAA(%al). */
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.global VG_(helper_DAA)
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VG_(helper_DAA):
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pushl %eax
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movl 8(%esp), %eax
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daa
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movl %eax, 8(%esp)
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popl %eax
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ret
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/* Bit scan forwards/reverse. Sets flags (??).
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On entry:
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value, replaced by result
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RA <- %esp
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*/
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.global VG_(helper_bsr)
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VG_(helper_bsr):
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pushl %eax
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movl 12(%esp), %eax
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bsrl 8(%esp), %eax
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movl %eax, 12(%esp)
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popl %eax
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ret
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.global VG_(helper_bsf)
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VG_(helper_bsf):
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pushl %eax
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movl 12(%esp), %eax
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bsfl 8(%esp), %eax
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movl %eax, 12(%esp)
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popl %eax
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ret
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/* 32-bit double-length shift left/right.
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On entry:
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amount
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src
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dst
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RA <- %esp
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*/
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.global VG_(helper_shldl)
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VG_(helper_shldl):
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pushl %eax
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pushl %ebx
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pushl %ecx
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movb 24(%esp), %cl
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movl 20(%esp), %ebx
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movl 16(%esp), %eax
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shldl %cl, %ebx, %eax
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movl %eax, 16(%esp)
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popl %ecx
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popl %ebx
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popl %eax
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ret
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.global VG_(helper_shldw)
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VG_(helper_shldw):
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pushl %eax
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pushl %ebx
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pushl %ecx
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movb 24(%esp), %cl
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movw 20(%esp), %bx
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movw 16(%esp), %ax
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shldw %cl, %bx, %ax
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movw %ax, 16(%esp)
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popl %ecx
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popl %ebx
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popl %eax
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ret
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.global VG_(helper_shrdl)
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VG_(helper_shrdl):
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pushl %eax
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pushl %ebx
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pushl %ecx
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movb 24(%esp), %cl
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movl 20(%esp), %ebx
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movl 16(%esp), %eax
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shrdl %cl, %ebx, %eax
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movl %eax, 16(%esp)
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popl %ecx
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popl %ebx
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popl %eax
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ret
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.global VG_(helper_shrdw)
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VG_(helper_shrdw):
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pushl %eax
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pushl %ebx
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pushl %ecx
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movb 24(%esp), %cl
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movw 20(%esp), %bx
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movw 16(%esp), %ax
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shrdw %cl, %bx, %ax
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movw %ax, 16(%esp)
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popl %ecx
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popl %ebx
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popl %eax
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ret
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/* Get the direction flag, and return either 1 or -1. */
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.global VG_(helper_get_dirflag)
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VG_(helper_get_dirflag):
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pushl %eax
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movl VGOFF_(m_dflag), %eax
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movl (%ebp, %eax, 4), %eax
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movl %eax, 8(%esp)
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popl %eax
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ret
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/* Clear/set the direction flag. */
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.global VG_(helper_CLD)
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VG_(helper_CLD):
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pushl %eax
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movl VGOFF_(m_dflag), %eax
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movl $1, (%ebp, %eax, 4)
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popl %eax
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ret
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.global VG_(helper_STD)
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VG_(helper_STD):
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pushl %eax
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movl VGOFF_(m_dflag), %eax
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movl $-1, (%ebp, %eax, 4)
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popl %eax
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ret
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/* Clear/set the carry flag. */
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.global VG_(helper_CLC)
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VG_(helper_CLC):
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clc
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ret
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.global VG_(helper_STC)
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VG_(helper_STC):
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stc
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ret
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/* Signed 32-to-64 multiply. */
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.globl VG_(helper_imul_32_64)
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VG_(helper_imul_32_64):
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pushl %eax
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pushl %edx
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movl 16(%esp), %eax
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imull 12(%esp)
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movl %eax, 16(%esp)
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movl %edx, 12(%esp)
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popl %edx
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popl %eax
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ret
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/* Signed 16-to-32 multiply. */
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.globl VG_(helper_imul_16_32)
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VG_(helper_imul_16_32):
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pushl %eax
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pushl %edx
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movw 16(%esp), %ax
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imulw 12(%esp)
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movw %ax, 16(%esp)
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movw %dx, 12(%esp)
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popl %edx
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popl %eax
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ret
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/* Signed 8-to-16 multiply. */
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.globl VG_(helper_imul_8_16)
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VG_(helper_imul_8_16):
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pushl %eax
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pushl %edx
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movb 16(%esp), %al
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imulb 12(%esp)
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movw %ax, 16(%esp)
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popl %edx
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popl %eax
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ret
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/* Unsigned 32-to-64 multiply. */
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.globl VG_(helper_mul_32_64)
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VG_(helper_mul_32_64):
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pushl %eax
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pushl %edx
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movl 16(%esp), %eax
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mull 12(%esp)
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movl %eax, 16(%esp)
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movl %edx, 12(%esp)
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popl %edx
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popl %eax
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ret
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/* Unsigned 16-to-32 multiply. */
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.globl VG_(helper_mul_16_32)
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VG_(helper_mul_16_32):
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pushl %eax
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pushl %edx
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movw 16(%esp), %ax
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mulw 12(%esp)
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movw %ax, 16(%esp)
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movw %dx, 12(%esp)
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popl %edx
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popl %eax
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ret
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/* Unsigned 8-to-16 multiply. */
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.globl VG_(helper_mul_8_16)
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VG_(helper_mul_8_16):
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pushl %eax
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pushl %edx
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movb 16(%esp), %al
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mulb 12(%esp)
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movw %ax, 16(%esp)
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popl %edx
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popl %eax
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ret
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/* Unsigned 64-into-32 divide. */
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.globl VG_(helper_div_64_32)
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VG_(helper_div_64_32):
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pushl %eax
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pushl %edx
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movl 16(%esp),%eax
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movl 12(%esp),%edx
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divl 20(%esp)
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movl %eax,16(%esp)
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movl %edx,12(%esp)
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popl %edx
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popl %eax
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ret
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/* Signed 64-into-32 divide. */
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.globl VG_(helper_idiv_64_32)
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VG_(helper_idiv_64_32):
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pushl %eax
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pushl %edx
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movl 16(%esp),%eax
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movl 12(%esp),%edx
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idivl 20(%esp)
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movl %eax,16(%esp)
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movl %edx,12(%esp)
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popl %edx
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popl %eax
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ret
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/* Unsigned 32-into-16 divide. */
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.globl VG_(helper_div_32_16)
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VG_(helper_div_32_16):
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pushl %eax
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pushl %edx
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movw 16(%esp),%ax
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movw 12(%esp),%dx
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divw 20(%esp)
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movw %ax,16(%esp)
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movw %dx,12(%esp)
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popl %edx
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popl %eax
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ret
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/* Signed 32-into-16 divide. */
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.globl VG_(helper_idiv_32_16)
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VG_(helper_idiv_32_16):
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pushl %eax
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pushl %edx
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movw 16(%esp),%ax
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movw 12(%esp),%dx
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idivw 20(%esp)
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movw %ax,16(%esp)
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movw %dx,12(%esp)
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popl %edx
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popl %eax
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ret
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/* Unsigned 16-into-8 divide. */
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.globl VG_(helper_div_16_8)
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VG_(helper_div_16_8):
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pushl %eax
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movw 12(%esp),%ax
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divb 16(%esp)
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movb %ah,12(%esp)
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movb %al,8(%esp)
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popl %eax
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ret
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/* Signed 16-into-8 divide. */
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.globl VG_(helper_idiv_16_8)
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VG_(helper_idiv_16_8):
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pushl %eax
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movw 12(%esp),%ax
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idivb 16(%esp)
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movb %ah,12(%esp)
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movb %al,8(%esp)
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popl %eax
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ret
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/* Undefined instruction (generates SIGILL) */
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.globl VG_(helper_undefined_instruction)
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VG_(helper_undefined_instruction):
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1: ud2
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jmp 1b
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##--------------------------------------------------------------------##
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##--- end vg_helpers.S ---##
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##--------------------------------------------------------------------##
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