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https://github.com/Zenithsiz/ftmemsim-valgrind.git
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58c1c98db4
Fix n32/n64 types mismatch in none, memcheck and helgrind tests. BZ issue - #345763. Contributed by: Dimitrije Nikolic, Aleksandar Rikalo, Tamara Vlahovic.
164 lines
7.8 KiB
C
164 lines
7.8 KiB
C
#include "const.h"
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#define TEST1(instruction, offset, mem) \
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{ \
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RegWord out = 0; \
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__asm__ __volatile__( \
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"move $t0, %1" "\n\t" \
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"move $t1, %2" "\n\t" \
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"daddu $t0, $t0, $t1" "\n\t" \
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"move $t1, $zero" "\n\t" \
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instruction" $t1, 0($t0)" "\n\t" \
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"move %0, $t1" "\n\t" \
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: "=r" (out) \
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: "r" (mem), "r" (offset) \
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: "t0", "t1" \
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); \
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printf("%s :: offset: 0x%x, out: 0x%" \
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FMT_REGWORD "x\n", instruction, \
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offset, out); \
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}
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#define TEST2(instruction, offset) \
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{ \
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RegWord out = 0; \
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RegWord outHI = 0; \
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__asm__ __volatile__( \
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"move $t0, %2" "\n\t" \
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"move $t1, %4" "\n\t" \
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"daddu $t0, $t0, $t1" "\n\t" \
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"ld $t3, 0($t0)" "\n\t" \
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"move $t1, %3" "\n\t" \
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"move $t2, %4" "\n\t" \
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"daddu $t1, $t1, $t2" "\n\t" \
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instruction" $t3, 0($t1)" "\n\t" \
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"li $t2, 7" "\n\t" \
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"nor $t2, $t2, $zero" "\n\t" \
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"and $t1, $t1, $t2" "\n\t" \
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"ld %0, 0($t1)" "\n\t" \
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"ld %1, 8($t1)" "\n\t" \
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: "=r" (out), "=r" (outHI) \
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: "r" (reg_val2) , "r" (reg_val_zero), "r" (offset) \
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: "t0", "t1", "t2", "t3" \
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); \
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printf("%s :: offset: 0x%x, out: 0x%" FMT_REGWORD "x, " \
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"outHI: 0x%" FMT_REGWORD "x\n", instruction, \
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offset, out, outHI); \
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}
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#define TEST3(instruction, offset, mem) \
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{ \
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RegWord out = 0; \
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__asm__ __volatile__( \
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"move $t0, %1" "\n\t" \
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"move $t1, %2" "\n\t" \
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"daddu $t0, $t0, $t1" "\n\t" \
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"dmtc1 $zero, $f0" "\n\t" \
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instruction" $f0, 0($t0)" "\n\t" \
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"dmfc1 %0, $f0" "\n\t" \
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: "=r" (out) \
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: "r" (mem) , "r" (offset) \
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: "t0", "t1", "$f0" \
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); \
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printf("%s :: offset: 0x%x, out: 0x%" \
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FMT_REGWORD "x\n", instruction, \
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offset, out); \
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}
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#define TEST3w(instruction, offset, mem) \
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{ \
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unsigned int out = 0; \
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__asm__ __volatile__( \
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"move $t0, %1" "\n\t" \
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"move $t1, %2" "\n\t" \
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"daddu $t0, $t0, $t1" "\n\t" \
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"dmtc1 $zero, $f0" "\n\t" \
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instruction" $f0, 0($t0)" "\n\t" \
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"mfc1 %0, $f0" "\n\t" \
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: "=r" (out) \
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: "r" (mem) , "r" (offset) \
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: "t0", "t1", "$f0" \
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); \
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printf("%s :: offset: 0x%x, out: 0x%x\n", \
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instruction, offset, out); \
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}
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#define TEST4(instruction, offset) \
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{ \
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RegWord out = 0; \
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__asm__ __volatile__( \
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"move $t0, %1" "\n\t" \
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"move $t1, %3" "\n\t" \
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"daddu $t0, $t0, $t1" "\n\t" \
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"ld $t2, 0($t0)" "\n\t" \
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"move $t0, %2" "\n\t" \
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"daddu $t0, $t0, $t1" "\n\t" \
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"dmtc1 $t2, $f0" "\n\t" \
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instruction" $f0, 0($t0)" "\n\t" \
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"ld %0, 0($t0)" "\n\t" \
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: "=r" (out) \
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: "r" (reg_val1) , "r" (reg_val_zero), "r" (offset) \
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: "t0", "t1", "t2", "$f0" \
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); \
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printf("%s :: offset: 0x%x, out: 0x%" FMT_REGWORD "x\n",\
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instruction, offset, out); \
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}
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#define TEST5(instruction, offset, mem) \
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{ \
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RegWord out = 0; \
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__asm__ __volatile__( \
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"move $t0, %1" "\n\t" \
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"move $t1, %2" "\n\t" \
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"dmtc1 $zero, $f0" "\n\t" \
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instruction" $f0, $t1($t0)" "\n\t" \
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"dmfc1 %0, $f0" "\n\t" \
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: "=r" (out) \
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: "r" (mem) , "r" (offset) \
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: "t0", "t1", "$f0" \
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); \
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printf("%s :: offset: 0x%x, out: 0x%" \
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FMT_REGWORD "x\n", instruction, \
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offset, out); \
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}
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#define TEST5w(instruction, offset, mem) \
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{ \
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unsigned int out = 0; \
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__asm__ __volatile__( \
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"move $t0, %1" "\n\t" \
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"move $t1, %2" "\n\t" \
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"dmtc1 $zero, $f0" "\n\t" \
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instruction" $f0, $t1($t0)" "\n\t" \
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"mfc1 %0, $f0" "\n\t" \
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: "=r" (out) \
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: "r" (mem) , "r" (offset) \
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: "t0", "t1", "$f0" \
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); \
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printf("%s :: offset: 0x%x, out: 0x%x\n", \
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instruction, offset, out); \
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}
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#define TEST6(instruction, offset) \
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{ \
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RegWord out = 0; \
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__asm__ __volatile__( \
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"move $t0, %1" "\n\t" \
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"move $t1, %3" "\n\t" \
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"daddu $t0, $t0, $t1" "\n\t" \
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"ld $t3, 0($t0)" "\n\t" \
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"move $t1, %2" "\n\t" \
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"move $t2, %3" "\n\t" \
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"daddu $t1, $t1, $t2" "\n\t" \
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"dmtc1 $t3, $f3" "\n\t" \
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"move $t0, %3" "\n\t" \
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instruction" $f3, $t0($t1)" "\n\t" \
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"ld %0, 0($t1)" "\n\t" \
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: "=r" (out) \
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: "r" (reg_val2) , "r" (reg_val_zero), "r" (offset) \
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: "t0", "t1", "t2", "t3" \
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); \
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printf("%s :: offset: 0x%x, out: 0x%" FMT_REGWORD "x\n",\
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instruction, offset, out); \
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}
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