Nicholas Nethercote 54f153c1da Cache simulation requires strict INCEIP updating so that the boundaries between ...

individual x86 instructions can be found when instrumenting UCode.  However,
EIP is not needed during execution, because the x86 instr addresses are copied
into the cost-centres.  So now they INCEIPs are removed during the
instrumentation step once their task is done.

This reduces running times by about 3--7%, and translation sizes by about 9%
(code expansion reduced from about 11x to about 10x).


git-svn-id: svn://svn.valgrind.org/valgrind/trunk@550

2002-08-01 08:09:51 +00:00

..

docs

Wibbles for 1.0.0.

2002-07-26 11:34:39 +00:00

cg_annotate.in

vg_annotate.in:

2002-06-10 15:31:16 +00:00

cg_main.c

Cache simulation requires strict INCEIP updating so that the boundaries between

2002-08-01 08:09:51 +00:00

cg_sim_D1.c

Removed the need for the user to generate a cache simulation -- now do

2002-06-08 13:36:03 +00:00

cg_sim_gen.c

This commit introduces two new UInstructions: CCALL_1_0, CCALL_2_0.

2002-07-28 09:53:34 +00:00

cg_sim_I1.c

Removed the need for the user to generate a cache simulation -- now do

2002-06-08 13:36:03 +00:00

cg_sim_L2.c

Removed the need for the user to generate a cache simulation -- now do

2002-06-08 13:36:03 +00:00

Makefile.am

Include valgrind.spec and valgrind.spec.in in tarballs.

2002-07-13 12:37:28 +00:00