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https://github.com/Zenithsiz/ftmemsim-valgrind.git
synced 2026-02-11 22:08:14 +00:00
Cavium toolchain defaults to soft-float, so it is important to enable full build of the test suite to work in that case as well. This boils down to protecting FPU-specific code segments with #if defined(__mips_hard_float) #endif git-svn-id: svn://svn.valgrind.org/valgrind/trunk@14572
72 lines
1.8 KiB
C
72 lines
1.8 KiB
C
#include <stdio.h>
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#include "macro_load_store.h"
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int main()
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{
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#if defined(__mips_hard_float)
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int i;
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int s1 = sizeof(int);
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int s2 = sizeof(unsigned long long);
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init_reg_val2();
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/**********************************************************************/
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/*-------------------------------LOAD---------------------------------*/
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/**********************************************************************/
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printf("--- LDC1 ---\n");
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for (i = 0; i < N*s1; i = i+8)
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TEST3("ldc1", i, reg_val1);
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for (i = 0; i < N*s2; i = i+8)
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TEST3("ldc1", i, reg_val2);
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printf("--- LDXC1 ---\n");
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for (i = 0; i < N*s1; i = i+8)
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TEST5("ldxc1", i, reg_val1);
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for (i = 0; i < N*s2; i = i+8)
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TEST5("ldxc1", i, reg_val2);
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printf("--- LWC1 ---\n");
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for (i = 0; i < N*s1; i = i+4)
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TEST3w("lwc1", i, reg_val1);
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for (i = 0; i < N*s2; i = i+4)
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TEST3w("lwc1", i, reg_val2);
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printf("--- LWXC1 ---\n");
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for (i = 0; i < N*s1; i = i+4)
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TEST5w("lwxc1", i, reg_val1);
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for (i = 0; i < N*s2; i = i+4)
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TEST5w("lwxc1", i, reg_val2);
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/**********************************************************************/
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/*-------------------------------STORE--------------------------------*/
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/**********************************************************************/
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init_reg_val_zero();
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printf("--- SDC1 ---\n");
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for (i = 0; i < N*s1; i = i+8) {
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TEST4("sdc1", i);
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}
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init_reg_val_zero();
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printf("--- SWC1 ---\n");
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for (i = 0; i < (N-1)*s1; i = i+4) {
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TEST4("swc1", i);
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}
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init_reg_val_zero();
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printf("--- SDXC1 ---\n");
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for (i = 0; i < N*s1; i = i+8) {
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TEST6("sdxc1", i);
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}
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init_reg_val_zero();
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printf("--- SWXC1 ---\n");
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for (i = 0; i < (N-1)*s1; i = i+4) {
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TEST6("swxc1", i);
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}
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#endif
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return 0;
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}
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