mirror of
https://github.com/Zenithsiz/ftmemsim-valgrind.git
synced 2026-02-17 08:04:36 +00:00
58c1c98db4
Fix n32/n64 types mismatch in none, memcheck and helgrind tests. BZ issue - #345763. Contributed by: Dimitrije Nikolic, Aleksandar Rikalo, Tamara Vlahovic.
142 lines
3.1 KiB
C
142 lines
3.1 KiB
C
#include <stdio.h>
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#include "pub_core_basics.h"
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#include "macro_load_store.h"
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int main()
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{
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int i;
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int s1 = sizeof(int);
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int s2 = sizeof(unsigned long long);
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init_reg_val2();
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/**********************************************************************/
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/*-------------------------------LOAD---------------------------------*/
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/**********************************************************************/
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/* lb */
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for (i = 0; i < N*s1; i++)
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TEST1("lb", i, reg_val1);
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for (i = 0; i < N*s2; i++)
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TEST1("lb", i, reg_val2);
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/* lbu */
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for (i = 0; i < N*s1; i++)
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TEST1("lbu", i, reg_val1);
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for (i = 0; i < N*s2; i++)
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TEST1("lbu", i, reg_val2);
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/* ld */
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for (i = 0; i < N*s1; i = i+8)
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TEST1("ld", i, reg_val1);
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for (i = 0; i < N*s2; i = i+8)
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TEST1("ld", i, reg_val2);
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#if (__mips_isa_rev < 6)
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/* ldl */
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for (i = 0; i < N*s1; i++)
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TEST1("ldl", i, reg_val1);
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for (i = 0; i < N*s2; i++)
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TEST1("ldl", i, reg_val2);
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/* ldr */
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for (i = 0; i < N*s1; i++)
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TEST1("ldr", i, reg_val1);
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for (i = 0; i < N*s2; i++)
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TEST1("ldr", i, reg_val2);
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#endif
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/* lh */
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for (i = 0; i < N*s1; i = i+2)
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TEST1("lh", i, reg_val1);
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for (i = 0; i < N*s2; i = i+2)
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TEST1("lh", i, reg_val2);
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/* lhu */
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for (i = 0; i < N*s1; i = i+2)
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TEST1("lhu", i, reg_val1);
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for (i = 0; i < N*s2; i = i+2)
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TEST1("lhu", i, reg_val2);
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/* lw */
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for (i = 0; i < N*s1; i = i+4)
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TEST1("lw", i, reg_val1);
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for (i = 0; i < N*s2; i = i+4)
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TEST1("lw", i, reg_val2);
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#if (__mips_isa_rev < 6)
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/* lwl */
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for (i = 0; i < N*s1; i++)
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TEST1("lwl", i, reg_val1);
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for (i = 0; i < N*s2; i++)
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TEST1("lwl", i, reg_val2);
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/* lwr */
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for (i = 0; i < N*s1; i++)
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TEST1("lwr", i, reg_val1);
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for (i = 0; i < N*s2; i++)
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TEST1("lwr", i, reg_val2);
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#endif
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/* lwu */
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for (i = 0; i < N*s1; i = i+4)
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TEST1("lwu", i, reg_val1);
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for (i = 0; i < N*s2; i = i+4)
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TEST1("lwu", i, reg_val2);
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/**********************************************************************/
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/*-------------------------------STORE--------------------------------*/
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/**********************************************************************/
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init_reg_val_zero();
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/* sb */
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for (i = 0; i < (N-1)*s2; i++)
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TEST2("sb", i);
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init_reg_val_zero();
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/* sd */
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for (i = 0; i < (N-1)*s2; i = i+8)
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TEST2("sd", i);
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#if (__mips_isa_rev < 6)
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init_reg_val_zero();
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/* sdl */
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for (i = 0; i < (N-1)*s2; i++)
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TEST2("sdl", i);
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init_reg_val_zero();
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/* sdr */
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for (i = 8; i < (N-1)*s2; i++)
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TEST2("sdr", i);
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#endif
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init_reg_val_zero();
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/* sh */
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for (i = 0; i < (N-1)*s2; i = i+2)
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TEST2("sh", i);
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init_reg_val_zero();
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/* sw */
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for (i = 0; i < (N-1)*s2; i = i+4)
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TEST2("sw", i);
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init_reg_val_zero();
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#if (__mips_isa_rev < 6)
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/* swl */
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for (i = 4; i < (N-1)*s2; i++)
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TEST2("swl", i);
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init_reg_val_zero();
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/* swr */
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for (i = 4; i < (N-1)*s2; i++)
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TEST2("swr", i);
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#endif
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return 0;
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}
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