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https://github.com/Zenithsiz/ftmemsim-valgrind.git
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200 lines
8.1 KiB
Plaintext
200 lines
8.1 KiB
Plaintext
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This file records register use conventions and info for the 4
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supported platforms (since it is ABI dependent). This is so as to
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avoid having to endlessly re-look up this info in ABI documents.
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-----------------------
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x86-linux
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~~~~~~~~~
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Reg Callee Arg
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Name Saves? Reg? Comment Vex-uses?
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--------------------------------------------------------------
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eax n n int[31:0] retreg y
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ebx y n y
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ecx n n y
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edx n n int[63:32] retreg y
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esi y n y
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edi y n y
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ebp y n & guest state
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esp reserved n/a n/a
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eflags n n/a y
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st0 n ? n fp retreg y
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st1-7 n ? n y
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xmm0-7 n ? n y
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amd64-linux
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~~~~~~~~~~~
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Reg Callee Arg
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Name Saves? Reg? Comment Vex-uses?
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-------------------------------------------------------------------
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rax n n int[63:0] retreg
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rbx y n y
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rcx n int#4
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rdx n int#3 int[127:64] retreg
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rsi n int#2 y
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rdi n int#1 y
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rbp y n & guest state
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rsp reserved n/a n/a
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r8 n int#5 y
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r9 n int#6 y
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r10 n ?
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r11 n jmp temporary
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r12-15 y y
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eflags n n/a y
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st0-7 n n long double retreg y
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xmm0 n fp#1 fp retreg
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xmm1 n fp#2 fp-high retreg
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xmm2-7 n fp#3-8 y (3-7)
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xmm8-15 n y (8-12)
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ppc32-linux
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~~~~~~~~~~~
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Reg Callee Arg
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Name Saves? Reg? Comment Vex-uses?
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-------------------------------------------------------------------
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r0 n n sometimes RAZ
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r1 y n stack pointer
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r2 n n
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r3 n int#1 int[31:0] retreg y
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r4 n int#2 also int retreg y
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r5 n int#3 y
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r6 n int#4 y
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r7 n int#5 y
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r8 n int#6 y
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r9 n int#7 y
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r10 n int#8 y
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r11 n y
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r12 n y
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r13 ?
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r14-28 y y
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r29 y reserved for dispatcher
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r30 y altivec spill temporary
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r31 y & guest state
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f0 n
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f1 n fp#1 fp retreg
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f2-8 n fp#2-8
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f9-13 n
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f14-31 y y (14-21)
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v0-v19 ?
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v20-31 y y (20-27,29)
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cr0-7
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lr y return address
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ctr n
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xer n
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fpscr
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ppc64-linux
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~~~~~~~~~~~
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TBD
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arm-linux
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~~~~~~~~~
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Reg Callee Arg
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Name Saves? Reg? Comment Vex-uses?
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--------------------------------------------------------------
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r0 int#1 int[31:0] retreg? avail
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r1 int#2 int[63:32] retreg? avail
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r2 int#3 avail
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r3 int#4 avail
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r4 y avail
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r5 y avail
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r6 y avail
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r7 y avail
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r8 y GSP
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r9 y (but only on Linux; not in general) avail
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r10 y avail
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r11 y avail
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r12 possibly used by linker? unavail
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r13(sp) unavail
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r14(lr) unavail
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r15(pc) unavail
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VFP: d8-d15 are callee-saved
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r12 (IP) is probably available for use as a caller-saved
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register; but instead we use it as an intermediate for
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holding the address for F32/F64 spills, since the VFP load/store
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insns have reg+offset forms for offsets only up to 1020, which
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often isn't enough.
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s390x-linux
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~~~~~~~~~~~
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Reg Callee Arg
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Name Saves? Reg? Comment Vex-uses?
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--------------------------------------------------------------
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r0 n see below unavail
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r1 n avail
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r2 n int#1 return value avail
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r3 n int#2 avail
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r4 n int#3 avail
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r5 n int#4 avail
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r6 y int#5 avail
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r7 y avail
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r8 y avail
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r9 y avail
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r10 y see below avail
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r11 y see below avail
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r12 y unavail VG_(dispatch_ctr)
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r13 y unavail gsp
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r14(lr) n unavail lr
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r15(sp) y unavail sp
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f0 n return value avail
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f1-f7 n avail
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f8-f11 y avail
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f12-f15 y see below avail
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When r0 is used as a base or index register its contents is
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ignored and the value 0 is used instead. This is the reason
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why VEX cannot use it.
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r10, r11 as well as f12-f15 are used as real regs during insn
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selection when register pairs are required.
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ppc32-aix5
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~~~~~~~~~~
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Reg Callee Arg
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Name Saves? Reg? Comment Vex-uses?
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-------------------------------------------------------------------
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r0 n n sometimes RAZ
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r1 y n stack pointer
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r2 n n TOC pointer
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r3 n int#1 int[31:0] retreg y
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r4 n int#2 also int retreg y
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r5 n int#3 y
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r6 n int#4 y
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r7 n int#5 y
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r8 n int#6 y
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r9 n int#7 y
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r10 n int#8 y
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r11 n "env pointer?!" y
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r12 n "exn handling" y
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r13 ? "reserved in 64-bit env"
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r14-28 y y
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r29 y reserved for dispatcher
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r30 y altivec spill temporary
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r31 y & guest state
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f0 n
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f1 n fp#1 fp retreg
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f2-13 n fp#2-13
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f14-31 y y (14-21)
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v0-v19 ?
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v20-31 y y (20-27,29)
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cr0-7
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lr y return address
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ctr n
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xer n
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fpscr
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