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https://github.com/Zenithsiz/ftmemsim-valgrind.git
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914f75de32
to add PPC64 LE support. The other two patches can be found in Bugzillas 334834 and 334836. The commit does not have a VEX commit associated with it. POWER PC, add initial Little Endian support The IBM POWER processor now supports both Big Endian and Little Endian. This patch renames the #defines with the name ppc64 to ppc64be for the BE specific code. This patch adds the Little Endian #define ppc64le to the Additionally, a few functions are renamed to remove BE from the name if the function is used by BE and LE. Functions that are BE specific have BE put in the name. The goals of this patch is to make sure #defines, function names and variables consistently use PPC64/ppc64 if it refers to BE and LE, PPC64BE/ppc64be if it is specific to BE, PPC64LE/ppc64le if it is LE specific. The patch does not break the code for PPC64 Big Endian. The test files memcheck/tests/atomic_incs.c, tests/power_insn_available.c and tests/power_insn_available.c are also updated to the new #define definition for PPC64 BE. Signed-off-by: Carl Love <carll@us.ibm.com> git-svn-id: svn://svn.valgrind.org/valgrind/trunk@14238
407 lines
9.9 KiB
C
407 lines
9.9 KiB
C
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/* Program which uses a happens-before edge to coordinate an access to
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variable 'shared_var' between two threads. The h-b edge is created
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by a custom (kludgesome!) mechanism and hence we need to use
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ANNOTATES_HAPPEN_{BEFORE,AFTER} to explain to Helgrind what's going
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on (else it reports a race). */
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#include <pthread.h>
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#include <stdio.h>
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#include <assert.h>
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#include "../../helgrind/helgrind.h"
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/* Todo: move all this do_acasW guff into a support library. It's
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useful for multiple tests, not just this one.
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XXX: all the do_acasW routines assume the supplied address
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is UWord (naturally) aligned. */
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typedef unsigned long int UWord;
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#if defined(VGA_ppc64be) || defined(VGA_ppc64le)
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// ppc64
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/* return 1 if success, 0 if failure */
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UWord do_acasW ( UWord* addr, UWord expected, UWord nyu )
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{
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UWord old, success;
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/* Fetch the old value, and set the reservation */
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__asm__ __volatile__ (
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"ldarx %0, 0,%1" "\n" // rD,rA,rB
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: /*out*/ "=b"(old)
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: /*in*/ "b"(addr)
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: /*trash*/ "memory","cc"
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);
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/* If the old value isn't as expected, we've had it */
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if (old != expected) return 0;
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/* otherwise try to stuff the new value in */
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__asm__ __volatile__(
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"stdcx. %2, 0,%1" "\n" // rS,rA,rB
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"mfcr %0" "\n\t"
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"srdi %0,%0,29" "\n\t"
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"andi. %0,%0,1" "\n"
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: /*out*/ "=b"(success)
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: /*in*/ "b"(addr), "b"(nyu)
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);
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assert(success == 0 || success == 1);
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return success;
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}
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#elif defined(VGA_ppc32)
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// ppc32
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/* return 1 if success, 0 if failure */
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UWord do_acasW ( UWord* addr, UWord expected, UWord nyu )
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{
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UWord old, success;
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/* Fetch the old value, and set the reservation */
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__asm__ __volatile__ (
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"lwarx %0, 0,%1" "\n" // rD,rA,rB
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: /*out*/ "=b"(old)
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: /*in*/ "b"(addr)
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: /*trash*/ "memory","cc"
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);
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/* If the old value isn't as expected, we've had it */
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if (old != expected) return 0;
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/* otherwise try to stuff the new value in */
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__asm__ __volatile__(
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"stwcx. %2, 0,%1" "\n" // rS,rA,rB
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"mfcr %0" "\n\t"
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"srwi %0,%0,29" "\n\t"
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"andi. %0,%0,1" "\n"
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: /*out*/ "=b"(success)
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: /*in*/ "b"(addr), "b"(nyu)
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);
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assert(success == 0 || success == 1);
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return success;
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}
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#elif defined(VGA_amd64)
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// amd64
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/* return 1 if success, 0 if failure */
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UWord do_acasW ( UWord* addr, UWord expected, UWord nyu )
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{
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UWord block[4] = { (UWord)addr, expected, nyu, 2 };
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__asm__ __volatile__(
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"movq 0(%%rsi), %%rdi" "\n\t" // addr
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"movq 8(%%rsi), %%rax" "\n\t" // expected
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"movq 16(%%rsi), %%rbx" "\n\t" // nyu
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"xorq %%rcx,%%rcx" "\n\t"
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"lock; cmpxchgq %%rbx,(%%rdi)" "\n\t"
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"setz %%cl" "\n\t"
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"movq %%rcx, 24(%%rsi)" "\n"
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: /*out*/
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: /*in*/ "S"(&block[0])
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: /*trash*/"memory","cc","rdi","rax","rbx","rcx"
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);
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assert(block[3] == 0 || block[3] == 1);
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return block[3] & 1;
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}
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#elif defined(VGA_x86)
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// x86
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/* return 1 if success, 0 if failure */
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UWord do_acasW ( UWord* addr, UWord expected, UWord nyu )
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{
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UWord block[4] = { (UWord)addr, expected, nyu, 2 };
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__asm__ __volatile__(
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"pushl %%ebx" "\n\t"
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"movl 0(%%esi), %%edi" "\n\t" // addr
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"movl 4(%%esi), %%eax" "\n\t" // expected
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"movl 8(%%esi), %%ebx" "\n\t" // nyu
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"xorl %%ecx,%%ecx" "\n\t"
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"lock; cmpxchgl %%ebx,(%%edi)" "\n\t"
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"setz %%cl" "\n\t"
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"movl %%ecx, 12(%%esi)" "\n\t"
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"popl %%ebx" "\n"
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: /*out*/
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: /*in*/ "S"(&block[0])
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: /*trash*/"memory","cc","edi","eax","ecx"
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);
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assert(block[3] == 0 || block[3] == 1);
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return block[3] & 1;
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}
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#elif defined(VGA_arm)
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// arm
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/* return 1 if success, 0 if failure */
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UWord do_acasW ( UWord* addr, UWord expected, UWord nyu )
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{
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UWord old, success;
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UWord block[2] = { (UWord)addr, nyu };
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/* Fetch the old value, and set the reservation */
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__asm__ __volatile__ (
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"ldrex %0, [%1]" "\n"
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: /*out*/ "=r"(old)
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: /*in*/ "r"(addr)
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);
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/* If the old value isn't as expected, we've had it */
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if (old != expected) return 0;
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/* otherwise try to stuff the new value in */
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__asm__ __volatile__(
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"ldr r4, [%1, #0]" "\n\t"
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"ldr r5, [%1, #4]" "\n\t"
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"strex r6, r5, [r4, #0]" "\n\t"
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"eor %0, r6, #1" "\n\t"
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: /*out*/ "=r"(success)
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: /*in*/ "r"(&block[0])
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: /*trash*/ "r4","r5","r6","memory"
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);
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assert(success == 0 || success == 1);
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return success;
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}
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#elif defined(VGA_arm64)
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// arm64
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/* return 1 if success, 0 if failure */
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UWord do_acasW ( UWord* addr, UWord expected, UWord nyu )
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{
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UWord old, success;
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UWord block[2] = { (UWord)addr, nyu };
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/* Fetch the old value, and set the reservation */
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__asm__ __volatile__ (
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"ldxr %0, [%1]" "\n"
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: /*out*/ "=r"(old)
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: /*in*/ "r"(addr)
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);
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/* If the old value isn't as expected, we've had it */
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if (old != expected) return 0;
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/* otherwise try to stuff the new value in */
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__asm__ __volatile__(
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"ldr x4, [%1, #0]" "\n\t"
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"ldr x5, [%1, #8]" "\n\t"
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"stxr w6, x5, [x4, #0]" "\n\t"
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"eor %0, x6, #1" "\n\t"
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: /*out*/ "=r"(success)
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: /*in*/ "r"(&block[0])
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: /*trash*/ "x4","x5","x6","memory"
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);
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assert(success == 0 || success == 1);
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return success;
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}
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#elif defined(VGA_s390x)
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// s390x
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/* return 1 if success, 0 if failure */
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UWord do_acasW(UWord* addr, UWord expected, UWord nyu )
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{
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int cc;
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__asm__ __volatile__ (
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"csg %2,%3,%1\n\t"
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"ipm %0\n\t"
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"srl %0,28\n\t"
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: /* out */ "=r" (cc)
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: /* in */ "Q" (*addr), "d" (expected), "d" (nyu)
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: "memory", "cc"
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);
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return cc == 0;
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}
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#elif defined(VGA_mips32)
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// mips32
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/* return 1 if success, 0 if failure */
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UWord do_acasW ( UWord* addr, UWord expected, UWord nyu )
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{
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UWord success;
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UWord block[3] = { (UWord)addr, nyu, expected};
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__asm__ __volatile__(
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".set noreorder" "\n\t"
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"lw $t0, 0(%1)" "\n\t"
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"lw $t2, 8(%1)" "\n\t"
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"lw $t3, 4(%1)" "\n\t"
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"ll $t1, 0($t0)" "\n\t"
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"bne $t1, $t2, exit_0" "\n\t"
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"nop" "\n\t"
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"sc $t3, 0($t0)" "\n\t"
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"move %0, $t3" "\n\t"
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"b exit" "\n\t"
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"nop" "\n\t"
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"exit_0:" "\n\t"
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"move %0, $zero" "\n\t"
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"exit:" "\n\t"
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: /*out*/ "=r"(success)
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: /*in*/ "r"(&block[0])
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: /*trash*/ "t0", "t1", "t2", "t3", "memory"
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);
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assert(success == 0 || success == 1);
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return success;
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}
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#elif defined(VGA_mips64)
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// mips64
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/* return 1 if success, 0 if failure */
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UWord do_acasW ( UWord* addr, UWord expected, UWord nyu )
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{
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UWord success;
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UWord block[3] = { (UWord)addr, nyu, expected};
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__asm__ __volatile__(
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".set noreorder" "\n\t"
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"ld $t0, 0(%1)" "\n\t"
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"ld $t2, 16(%1)" "\n\t"
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"ld $t3, 8(%1)" "\n\t"
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"ll $t1, 0($t0)" "\n\t"
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"bne $t1, $t2, exit_0" "\n\t"
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"nop" "\n\t"
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"sc $t3, 0($t0)" "\n\t"
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"move %0, $t3" "\n\t"
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"b exit" "\n\t"
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"nop" "\n\t"
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"exit_0:" "\n\t"
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"move %0, $zero" "\n\t"
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"exit:" "\n\t"
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: /*out*/ "=r"(success)
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: /*in*/ "r"(&block[0])
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: /*trash*/ "t0", "t1", "t2", "t3", "memory"
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);
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assert(success == 0 || success == 1);
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return success;
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}
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#endif
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void atomic_incW ( UWord* w )
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{
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while (1) {
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UWord old = *w;
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UWord nyu = old + 1;
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UWord ok = do_acasW( w, old, nyu );
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if (ok) break;
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};
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}
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#if 0
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#define NNN 1000000
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void* thread_fn ( void* arg )
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{
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UWord* w = (UWord*)arg;
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int i;
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for (i = 0; i < NNN; i++)
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atomic_incW( w );
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return NULL;
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}
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int main ( void )
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{
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int r;
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//ANNOTATE_HAPPENS_BEFORE(0);
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//return 0;
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UWord w = 0;
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pthread_t t1, t2;
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r= pthread_create( &t1, NULL, &thread_fn, (void*)&w ); assert(!r);
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r= pthread_create( &t2, NULL, &thread_fn, (void*)&w ); assert(!r);
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r= pthread_join( t1, NULL ); assert(!r);
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r= pthread_join( t2, NULL ); assert(!r);
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printf("result = %lu\n", w );
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return 0;
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}
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#endif
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int shared_var = 0; // is not raced upon
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void delayXms ( int i )
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{
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struct timespec ts = { 0, 1 * 1000 * 1000 };
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// We do the sleep in small pieces to have scheduling
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// events ensuring a fair switch between threads, even
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// without --fair-sched=yes. This is a.o. needed for
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// running this test under an outer helgrind or an outer
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// sgcheck.
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while (i > 0) {
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nanosleep(&ts, NULL);
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i--;
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}
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}
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void do_wait ( UWord* w )
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{
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UWord w0 = *w;
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UWord volatile * wV = w;
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while (*wV == w0)
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delayXms(1); // small sleeps, ensuring context switches
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ANNOTATE_HAPPENS_AFTER(w);
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}
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void do_signal ( UWord* w )
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{
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ANNOTATE_HAPPENS_BEFORE(w);
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atomic_incW(w);
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}
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void* thread_fn1 ( void* arg )
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{
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UWord* w = (UWord*)arg;
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delayXms(500); // ensure t2 gets to its wait first
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shared_var = 1; // first access
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do_signal(w); // cause h-b edge to second thread
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delayXms(500);
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return NULL;
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}
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void* thread_fn2 ( void* arg )
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{
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UWord* w = (UWord*)arg;
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do_wait(w); // wait for h-b edge from first thread
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shared_var = 2; // second access
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delayXms(500);
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return NULL;
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}
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int main ( void )
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{
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int r;
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UWord w = 0;
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pthread_t t1, t2;
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r= pthread_create( &t1, NULL, &thread_fn1, (void*)&w ); assert(!r);
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r= pthread_create( &t2, NULL, &thread_fn2, (void*)&w ); assert(!r);
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r= pthread_join( t1, NULL ); assert(!r);
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r= pthread_join( t2, NULL ); assert(!r);
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return 0;
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}
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