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https://github.com/Zenithsiz/ftmemsim-valgrind.git
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78 lines
2.9 KiB
C
78 lines
2.9 KiB
C
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/*--------------------------------------------------------------------*/
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/*--- Asm-only TransTab stuff. pub_core_transtab_asm.h ---*/
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/*--------------------------------------------------------------------*/
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/*
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This file is part of Valgrind, a dynamic binary instrumentation
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framework.
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Copyright (C) 2000-2013 Julian Seward
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jseward@acm.org
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This program is free software; you can redistribute it and/or
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modify it under the terms of the GNU General Public License as
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published by the Free Software Foundation; either version 2 of the
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License, or (at your option) any later version.
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This program is distributed in the hope that it will be useful, but
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WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with this program; if not, write to the Free Software
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Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA
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02111-1307, USA.
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The GNU General Public License is contained in the file COPYING.
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*/
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#ifndef __PUB_CORE_TRANSTAB_ASM_H
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#define __PUB_CORE_TRANSTAB_ASM_H
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/* Constants for the fast translation lookup cache. It is a direct
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mapped cache, with 2^VG_TT_FAST_BITS entries.
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On x86/amd64, the cache index is computed as
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'address[VG_TT_FAST_BITS-1 : 0]'.
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On ppc32/ppc64/mips32/mips64/arm64, the bottom two bits of
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instruction addresses are zero, which means that function causes
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only 1/4 of the entries to ever be used. So instead the function
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is '(address >>u 2)[VG_TT_FAST_BITS-1 : 0]' on those targets.
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On ARM we shift by 1, since Thumb insns can be of size 2, hence to
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minimise collisions and maximise cache utilisation we need to take
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into account all but the least significant bit.
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On s390x the rightmost bit of an instruction address is zero.
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For best table utilization shift the address to the right by 1 bit. */
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#define VG_TT_FAST_BITS 15
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#define VG_TT_FAST_SIZE (1 << VG_TT_FAST_BITS)
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#define VG_TT_FAST_MASK ((VG_TT_FAST_SIZE) - 1)
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/* This macro isn't usable in asm land; nevertheless this seems
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like a good place to put it. */
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#if defined(VGA_x86) || defined(VGA_amd64)
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# define VG_TT_FAST_HASH(_addr) ((((UWord)(_addr)) ) & VG_TT_FAST_MASK)
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#elif defined(VGA_s390x) || defined(VGA_arm)
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# define VG_TT_FAST_HASH(_addr) ((((UWord)(_addr)) >> 1) & VG_TT_FAST_MASK)
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#elif defined(VGA_ppc32) || defined(VGA_ppc64) || defined(VGA_mips32) \
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|| defined(VGA_mips64) || defined(VGA_arm64)
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# define VG_TT_FAST_HASH(_addr) ((((UWord)(_addr)) >> 2) & VG_TT_FAST_MASK)
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#else
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# error "VG_TT_FAST_HASH: unknown platform"
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#endif
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#endif // __PUB_CORE_TRANSTAB_ASM_H
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/*--------------------------------------------------------------------*/
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/*--- end ---*/
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/*--------------------------------------------------------------------*/
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