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https://github.com/Zenithsiz/ftmemsim-valgrind.git
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60d9b410d4
of the L2 cache. This is to accommodate machines with three levels of cache. We still only simulate two levels, the first and the last. git-svn-id: svn://svn.valgrind.org/valgrind/trunk@11404
21 lines
248 B
Plaintext
21 lines
248 B
Plaintext
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Events : Ir Dr Dw I1mr D1mr D1mw ILmr DLmr DLmw ILdmr DLdmr DLdmw
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Collected :
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I refs:
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I1 misses:
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LLi misses:
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I1 miss rate:
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LLi miss rate:
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D refs:
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D1 misses:
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LLd misses:
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D1 miss rate:
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LLd miss rate:
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LL refs:
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LL misses:
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LL miss rate:
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