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e2419dbd5dc0da3fc28cfbb5407549cde67b0ced
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636 Commits

Author SHA1 Message Date
Cerion Armour-Brown
e2419dbd5d added padding to VexGuestArmState 
git-svn-id: svn://svn.valgrind.org/vex/trunk@642
 2004-12-10 10:46:16 +00:00
Cerion Armour-Brown
79595c01ac Finished dis_branch, so we get IR code for a complete bb now - yay! 
Fixed a bunch of type errors picked up by the sanity checker



git-svn-id: svn://svn.valgrind.org/vex/trunk@641
 2004-12-10 10:18:58 +00:00
Julian Seward
cca70dff12 Finish almost all SSE2 integer instructions. (!) 
git-svn-id: svn://svn.valgrind.org/vex/trunk@640
 2004-12-10 01:48:18 +00:00
Julian Seward
e5119dcd20 x86 host/guest: SSE2 integer shifts and subtracts 
git-svn-id: svn://svn.valgrind.org/vex/trunk@639
 2004-12-09 23:25:14 +00:00
Cerion Armour-Brown
09d1a87ef6 Reworked dis_loadstore_mult(): load/store multiple 
Reworked data processing instrs:
 - all dpi's are dealt with in dis_dataproc()
 - dis_shifter_op() finds the shift expression
   - directly if 'immediate', else via dis_shift(), dis_rotate
   - returns the shifter_carry_out
     (would rather not to do this... how to avoid it?!)

Added dis_loadstore_w_ub : load/store word|unsigned byte

First stab at dis_branch(), but not there yet.

Laid out disInstr to parse the entire arm instruction set.
 - was the easiest thing to do to avoid all the undefined and not-yet-implemented instructions.

Some work on flag calculations - not yet right!




git-svn-id: svn://svn.valgrind.org/vex/trunk@638
 2004-12-09 19:04:57 +00:00
Julian Seward
90969d6910 x86 guest/host: implement a whole bunch of SSE2 integer insns 
git-svn-id: svn://svn.valgrind.org/vex/trunk@637
 2004-12-09 03:44:34 +00:00
Julian Seward
f273b21842 IR level for support of 128 integer SIMD operations. Use this to do 
SSE2 integer operations (x86 guest/host).



git-svn-id: svn://svn.valgrind.org/vex/trunk@636
 2004-12-09 00:39:32 +00:00
Julian Seward
a310e39a1f Delete commented-out bits of the old UCode insn decoder. 
git-svn-id: svn://svn.valgrind.org/vex/trunk@635
 2004-12-08 17:01:23 +00:00
Julian Seward
b4c4fd0ab9 x86 guest: finish SSE2 floating point insns. 
git-svn-id: svn://svn.valgrind.org/vex/trunk@634
 2004-12-08 14:37:10 +00:00
Julian Seward
025d4369bb x86 guest: another stack of SSE2 insns. 
git-svn-id: svn://svn.valgrind.org/vex/trunk@633
 2004-12-08 12:31:22 +00:00
Julian Seward
a234d1dc97 x86 guest: Implement a whole bunch of SSE2 instructions, mostly 
int-float conversions.  Very repetitive.



git-svn-id: svn://svn.valgrind.org/vex/trunk@632
 2004-12-07 19:02:18 +00:00
Julian Seward
43641ec037 Redundant-Get elimination: only do the substitution when the types 
match.  Not doing so leads to incorrectly typed IR.


git-svn-id: svn://svn.valgrind.org/vex/trunk@631
 2004-12-07 19:00:57 +00:00
Julian Seward
867ab938c4 Copy-n-paste 32x4 floating point stuff into 64x2 floating point stuff so 
as to form a basis for SSE2 floating point support.



git-svn-id: svn://svn.valgrind.org/vex/trunk@630
 2004-12-07 11:16:04 +00:00
Julian Seward
c73a5a146c x86 guest: Implement various insns: 
ldmxcsr/stmxcsr
   fldenv/fstenv
   prefetch of various flavours (no-op for us)
   fclex (no-op for us)
   Some segment reg stuff, but nothing usable yet


git-svn-id: svn://svn.valgrind.org/vex/trunk@629
 2004-12-06 14:29:12 +00:00
Julian Seward
8970b347b9 Tests for x86 fldenv/fstenv; also fix error in frstor test. 
git-svn-id: svn://svn.valgrind.org/vex/trunk@628
 2004-12-06 14:26:28 +00:00
Julian Seward
3ffae38d0e Program for testing setting of MXCSR. 
git-svn-id: svn://svn.valgrind.org/vex/trunk@627
 2004-12-06 12:15:05 +00:00
Julian Seward
c70e19435b Fix bug exposed by improved insn_sse test. 
git-svn-id: svn://svn.valgrind.org/vex/trunk@626
 2004-12-06 00:36:25 +00:00
Julian Seward
ed9a19d140 Another test case, containing a lot of FP code, which generally stresses 
iropt quite a lot.


git-svn-id: svn://svn.valgrind.org/vex/trunk@625
 2004-12-06 00:00:04 +00:00
Julian Seward
204930a489 Move to new place. 
git-svn-id: svn://svn.valgrind.org/vex/trunk@624
 2004-12-05 23:54:32 +00:00
Julian Seward
f7d387c46d Contains most fpu, mmx and sse1 insns. 
git-svn-id: svn://svn.valgrind.org/vex/trunk@623
 2004-12-05 23:53:22 +00:00
Julian Seward
ae14891105 Make small procedures to add/sub small amounts from esp. 
git-svn-id: svn://svn.valgrind.org/vex/trunk@621
 2004-12-05 21:22:38 +00:00
Julian Seward
15c112611b Finish SSE1 instructions! Finallyatlast. 
git-svn-id: svn://svn.valgrind.org/vex/trunk@620
 2004-12-05 19:29:45 +00:00
Julian Seward
6e6f665b0f Fix a load of confusion with SSE scalar float insns and memory. 
git-svn-id: svn://svn.valgrind.org/vex/trunk@619
 2004-12-05 15:42:05 +00:00
Julian Seward
f76dbe65ed Even more SSE insns. 
git-svn-id: svn://svn.valgrind.org/vex/trunk@618
 2004-12-05 02:47:40 +00:00
Julian Seward
1b7069f596 x86 host/guest: even more SSE instructions 
git-svn-id: svn://svn.valgrind.org/vex/trunk@617
 2004-12-04 20:33:02 +00:00
Julian Seward
2875f2e1f9 Rationalisation/cleanup of float to/from int conversions and rounding 
modes associated with them.



git-svn-id: svn://svn.valgrind.org/vex/trunk@616
 2004-12-04 14:36:09 +00:00
Julian Seward
b69ba13305 x86 guest/host: a whole bunch more SSE instructions. 
git-svn-id: svn://svn.valgrind.org/vex/trunk@615
 2004-12-04 01:38:37 +00:00
Julian Seward
236f79b0a1 Add a bunch of easy SSE insns. 
git-svn-id: svn://svn.valgrind.org/vex/trunk@614
 2004-12-03 20:08:31 +00:00
Julian Seward
f172787ae4 Mucho messing around with x86 FP/SSE rounding modes etc. As a result 
implement a bunch of SSE float-int conversion insns.



git-svn-id: svn://svn.valgrind.org/vex/trunk@613
 2004-12-03 19:43:31 +00:00
Cerion Armour-Brown
347ec43cec cleaned up dis_mov & dis_shift_lsl, and made a stab at dis_ldm_stm: load/store multiple 
git-svn-id: svn://svn.valgrind.org/vex/trunk@612
 2004-12-03 18:54:08 +00:00
Julian Seward
28f8f4c261 Try to reduce the number of warnings gcc gives. 
git-svn-id: svn://svn.valgrind.org/vex/trunk@611
 2004-12-03 11:55:29 +00:00
Cerion Armour-Brown
713fee1473 trying to get shift_lsl to work + cleaned up a little 
git-svn-id: svn://svn.valgrind.org/vex/trunk@610
 2004-12-03 11:16:42 +00:00
Julian Seward
40c52285d1 Add another comment and actually complete the commit message :-) 
git-svn-id: svn://svn.valgrind.org/vex/trunk@609
 2004-12-02 23:36:20 +00:00
Julian Seward
415c39f175 Try to answer a few q 
git-svn-id: svn://svn.valgrind.org/vex/trunk@608
 2004-12-02 23:35:18 +00:00
Cerion Armour-Brown
ef19019311 Ceri's first attempts at figuring out what the heck is going on! 
git-svn-id: svn://svn.valgrind.org/vex/trunk@607
 2004-12-02 20:19:22 +00:00
Julian Seward
8023366e99 x86 guest/host: do SSE comiss instruction 
git-svn-id: svn://svn.valgrind.org/vex/trunk@606
 2004-12-02 18:16:33 +00:00
Julian Seward
5c6c0cc4b0 x86 guest/host: do SSE comparisons. 
To make this easier, add to IRConst a new kind of literal -- 
a 128-bit literal specified by a 16-bit value.  Each bit of the
latter is defines one byte of the 128-bit value, either 0x00 or
0xFF.



git-svn-id: svn://svn.valgrind.org/vex/trunk@605
 2004-12-02 16:16:11 +00:00
Julian Seward
6851682a46 x86 host: make a start on SSE code generation. 
git-svn-id: svn://svn.valgrind.org/vex/trunk@604
 2004-12-01 23:19:36 +00:00
Julian Seward
8464fc72e9 In the back end, rename the register classes (in enum HRegClass) more 
consistently, in preparation for SSE instruction selection on x86
host.



git-svn-id: svn://svn.valgrind.org/vex/trunk@603
 2004-12-01 02:24:44 +00:00
Julian Seward
76d8f00edc Make a start on SSE for x86 guest. 
git-svn-id: svn://svn.valgrind.org/vex/trunk@602
 2004-11-30 18:51:59 +00:00
Nicholas Nethercote
45357238cd Added AMD64 skeleton, just defining LibVEX_GuestAMD64_initialise(). 
git-svn-id: svn://svn.valgrind.org/vex/trunk@601
 2004-11-30 15:56:47 +00:00
Julian Seward
0e29835d76 Loop unroller: do not unroll loops in which the conditional branch is 
not Ijk_Boring, as that will cause events that should be passed to the
caller's scheduler, not to be.



git-svn-id: svn://svn.valgrind.org/vex/trunk@600
 2004-11-30 13:40:29 +00:00
Julian Seward
f5a2a1606e Add -Wmissing-prototypes as a flag. 
git-svn-id: svn://svn.valgrind.org/vex/trunk@599
 2004-11-30 13:37:21 +00:00
Julian Seward
4f365980c3 guest x86: fix x87 FP rounding modes enough so that 
none/tests/x86/insn_fpu works correctly.



git-svn-id: svn://svn.valgrind.org/vex/trunk@598
 2004-11-30 13:18:37 +00:00
Julian Seward
a5ff6638bb guest x87: Add enough x87 FP gunk to get through 
none/tests/x86/insn_fpu without dying.



git-svn-id: svn://svn.valgrind.org/vex/trunk@597
 2004-11-30 12:30:11 +00:00
Nicholas Nethercote
b1be842d36 Make Valgrind's AMD64 and ARM ports compile again. 
git-svn-id: svn://svn.valgrind.org/vex/trunk@596
 2004-11-30 11:37:48 +00:00
Julian Seward
26338fd250 Create a new mechanism: "emulation warnings", which is a way for Vex 
to report to whatever is using it that it cannot emulate precisely.
Net result is that a bb can exit with the guest state pointer set to
VEX_TRC_EMWARN.  In this case, the (mandatory) guest state psuedo-reg
called "guest_EMWARN" holds a value of type VexEmWarn, indicating the
kind of problem encounted.

Use this to warn about approximations in the x87 FPU simulation:
unmasked exceptions not supported, round to +inf/-inf not supported,
precisions other than 80-bit not supported.



git-svn-id: svn://svn.valgrind.org/vex/trunk@595
 2004-11-29 19:57:54 +00:00
Nicholas Nethercote
9167c47f04 Added %rip to the AMD64 guest state. 
git-svn-id: svn://svn.valgrind.org/vex/trunk@594
 2004-11-28 16:05:46 +00:00
Julian Seward
2e5eae7fe5 x86g_dirtyhelper_CPUID: Claim to be a P55C (Intel Pentium/MMX) 
git-svn-id: svn://svn.valgrind.org/vex/trunk@593
 2004-11-26 19:34:34 +00:00
Julian Seward
c9f5e132ec x86 guest: finish off MMX instructions. Blargh. 
git-svn-id: svn://svn.valgrind.org/vex/trunk@592
 2004-11-26 19:15:38 +00:00