Tests that are testing mips instructions c.cond.s and c.cond.d have been added in none/tests/mips32.
git-svn-id: svn://svn.valgrind.org/valgrind/trunk@13839
Tests for 64bit FPU instructions on MIPS32 platforms.
Some mips instructions can cause SIGILL (Illegal instruction),
so we need to add SIGILL signal and a proper handler for that signal.
git-svn-id: svn://svn.valgrind.org/valgrind/trunk@13817
also allows us to drop the loop that was supposed to give the child a
chance to exit as the pclose will wait properly for the child.
Fix from Ivo Raisr on BZ#331255
git-svn-id: svn://svn.valgrind.org/valgrind/trunk@13813
Tests that should be executed on MIPS64 platforms that support lwx, ldx
and lbux.
Relevant VEX change - r2819.
Patch by Zahid Anwar, with some changes.
Related to Bugzilla issue 326444. It closes this issue now.
git-svn-id: svn://svn.valgrind.org/valgrind/trunk@13808
Read-memory tests are endian sensitive.
Add BE version of cvm_lx_ins.stdout.exp that has been tested on
Cavium Octeon II in BE mode.
Related to Bugzilla issue 326444.
git-svn-id: svn://svn.valgrind.org/valgrind/trunk@13805
instruction: dcbzl" submitted by Anmol P. Paralkar <paralkar@freescale.com>
The patch adds the following files:
none/tests/ppc64/data-cache-instructions.vgtest
none/tests/ppc64/data-cache-instructions.c
none/tests/ppc64/data-cache-instructions.stdout.exp
none/tests/ppc64/data-cache-instructions.stderr.exp
none/tests/ppc32/data-cache-instructions.stdout.exp
none/tests/ppc32/data-cache-instructions.c
none/tests/ppc32/data-cache-instructions.vgtest
none/tests/ppc32/data-cache-instructions.stderr.exp
tests/power_insn_available.c
The following files are modified:
none/tests/ppc32/Makefile.am
none/tests/ppc64/Makefile.am
tests/Makefile.am
git-svn-id: svn://svn.valgrind.org/valgrind/trunk@13791
Tests for lhux, lwux, and lbx for Cavium Octeon II.
Patch by Zahid Anwar, with changes.
Related to Bugzilla issue 326444.
git-svn-id: svn://svn.valgrind.org/valgrind/trunk@13786
instructions.
The patch also adds ppc32 and ppc64 test cases for the instructions.
The patch is a fix for bugzilla 329956 "valgrind crashes when lmw/stmw instructions are used on ppc64".
The VEX code commit is 2802
git-svn-id: svn://svn.valgrind.org/valgrind/trunk@13780
Fix some typo error and some errors in tests that was discovered while running Valgrind on MIPS/Android.
In some cases initial FCSR value wasn't being set properly.
git-svn-id: svn://svn.valgrind.org/valgrind/trunk@13746
make dist will not copy header files if they are not explicitly listed
in EXTRA_DIST. This change adds missing header files from none/test/mips64.
git-svn-id: svn://svn.valgrind.org/valgrind/trunk@13701
vaddcuq, vadduqm, vaddecuq, vaddeuqm,
vsubcuq, vsubuqm, vsubecuq, vsubeuqm,
vbpermq and vgbbd.
The completes adding the Power ISA 2.07 support.
Bugzilla 325816
VEX commit id 2790
git-svn-id: svn://svn.valgrind.org/valgrind/trunk@13653
A previous commit had decreased to 6 (on android) and increased to 16
(other platforms) the nr of sectors in the translation cache.
This patch adds a command line option to let the user specify
the nr of sectors as e.g. 16 sectors might be a lot and cause
an out of memory for some workloads or might be too small for
huge executable or executables using a lot of shared libs.
git-svn-id: svn://svn.valgrind.org/valgrind/trunk@13652
This commit adds the testcases for the following instructions:
vpmsumb, vpmsumh, vpmsumw, vpmsumd, vpermxor, vcipher, vcipherlast,
vncipher, vncipherlast, vsbox,
vclzb, vclzw, vclzh, vclzd,
vpopcntb, vpopcnth, vpopcntw, vpopcntd,
vnand, vorc, veqv,
vshasigmaw, vshasigmad,
bcdadd, bcdsub
The VEX commit that added the support for the above instructions was
commit 2789.
The patch is for Bugzilla 325628
git-svn-id: svn://svn.valgrind.org/valgrind/trunk@13646
Change the input values so that the binary values
is representing exactly the same float values.
git-svn-id: svn://svn.valgrind.org/valgrind/trunk@13632
The initial Transactional Memory instruction patch did not include the two
privileged (OS) instructions treclaim and trechkpt. VEX commit 2784 added
the support for these two instructions.
This patch adds a touch test to make sure all of the POWER Transactional
memory instrutions are recognized by Valgrind. All of the the Transactional
Memory instructions, with the exception of tbegin, are treated as NOPs in the
first implementation. The tbegin instruction causes the transaction to fail
thus no additional Transactional Memory instructions on the successful
transaction path would be executed in a real program. This test just makes
sure each instruction is actually recognized by Valgrind.
The patch if for Bugzilla 325751.
git-svn-id: svn://svn.valgrind.org/valgrind/trunk@13630
Those tests were rejected by clang and according to the
analysis below by Tom Hughes do not add anything new.
Analysis:
I'm not 100% sure that clang is right though - the Intel manual
clearly describes that argument as "reg" rather than "r32" which
is why I will have included the 64 bit version in the test. It also says:
"The upper bits of r32 or r64 is zeroed."
and:
"If the destination operand is a general-purpose register, the
default operand size is 64-bits in 64-bit mode."
which basically means that REX.W is implied for this op and there is
no way to encode a 32 bit version when running in 64 bit mode.
So in principle you could encode it as:
44 0f c5 ce 00 pextrw $0x0,%mm6,%r9d
or:
4c 0f c5 ce 00 pextrw $0x0,%mm6,%r9
but in fact gcc assembles both versions to the first form.
Equally you could argue that as REX.W is implied both versions
should disassemble as %r9.
So I think clang is being overly picky, and if it was only going to
accept one version I would argue it should be %r9 not %r9d!
In practical terms dropping the second set of tests doesn't lose us anything though.
git-svn-id: svn://svn.valgrind.org/valgrind/trunk@13614
This patch adds testcases for the following instructions added
in phase 4. The instructions are for doing various arithmetic,
logic, and load/store VSX operations:
xscvsxdsp xscvuxdsp xsaddsp xssubsp xsdivsp xsmaddasp xsmaddmsp
xsmsubasp xsmsubmsp xsnmaddasp xsnmaddmsp xsnmsubasp xsnmsubmsp
xsmulsp xssqrtsp xsresp xsrsqrtesp xsrsp xxlorc xxlnand xxleqv
lxsiwzx lxsiwax lxsspx stxsiwx stxsspx
Signed-off-by: Maynard Johnson <maynardj@us.ibm.com>
VEX commit for the instruction support r2781
Bugzilla 325477
git-svn-id: svn://svn.valgrind.org/valgrind/trunk@13611
as suggested by John Reiser and Greg Parker.
It seems that GCC has a more relaxed attitude about what it accepts
as valid input.
git-svn-id: svn://svn.valgrind.org/valgrind/trunk@13610
compilers as the -mhtm flag is not known. The patch fixes the makefile
issue and addes #defines to the testcase code.
The testcase was added in valgrind commit 13607.
The bugzilla for adding the TM instruction support is 323803
git-svn-id: svn://svn.valgrind.org/valgrind/trunk@13608
The test case for the transaction memory instructions executes the
failure path when run under valgrind. This is since the initial
Transaction Memory implemnetation is to simply fail the TBEGIN instruction
forcing the execution flow to take the failure path. When the
test case is executed on the real hardware, the success path will
be taken. Only the TBEGIN instruction actually does anything. All other
transactional memory instructions are NOPs since only failure path is executed
and it assumed to not have any transactional memory instructions on it.
Signed-off-by: Carl Love <cel@us.ibm.com>
VEX commit revision 2780
Bugzilla 323803
git-svn-id: svn://svn.valgrind.org/valgrind/trunk@13607
This patch adds testcases to an existing testcase
source file to test the new instructions which were
added to VEX support in the phase 3 ISA 2.07 code patch.
The patch also makes a small change to memcheck's
vbit tester code to allow successful execution.
Signed-off-by: Maynard Johnson <maynardj@us.ibm.com>
Bugzilla 324894. Corresponding VEX commit 2779
git-svn-id: svn://svn.valgrind.org/valgrind/trunk@13594
