Commit Graph

5 Commits

Author SHA1 Message Date
Nicholas Nethercote
f1689b96db Changed lots of files for the new core/ + skin/ directory structure:
- changed lots of Makefile.am files
   - changed configure.in
   - changed lots of #include lines for changed file names
   - changed lots of file headers n footers for changed file names
   - changed vg_regtest to handle new directory structure -- recursively
     traverses subdirectories for .vgtest test files
   - changed lots of paths in memcheck/ regression test expected outputs


git-svn-id: svn://svn.valgrind.org/valgrind/trunk@1090
2002-09-23 11:21:57 +00:00
Nicholas Nethercote
afebe61b37 Files updated, added and removed in order to turn the ERASER branch into HEAD
git-svn-id: svn://svn.valgrind.org/valgrind/trunk@1086
2002-09-23 09:36:25 +00:00
Nicholas Nethercote
b859182c44 Removed the need for the user to generate a cache simulation -- now do
automatic cache configuration detection using the CPUID instruction.
This can be overridden from the command-line if necessary.

vg_include.h:
    - added the cache_t type and UNDEFINED_CACHE macro

    - added command line args (of type cache_t) allowing manual override of
      I1/D1/L2 configuration

    - added log2(), which is generally useful

vg_main.c, valgrind.in, cachegrind.in:
    - added handling of the new --{I1,D1,L2}=<size>,<assoc>,<line_size>
      options

vg_cachesim.c:
    - lots of stuff for auto-detecting cache configuration with CPUID.
      Only handles Intel and AMD chips at the moment, and possibly not all of
      them.  Falls back onto defaults if anything goes wrong, and the configs
      can be manually overridden from the command line anyway.

    - now not printing cache summary stats if verbosity == 0.  Still writing
      cachegrind.out, though.

vg_cachesim_gen.c:
    - new file containing stuff shared by the I1/D1/L2 simulations

vg_cachesim_{I1,D1,L2}:
    - removed most of it;  each now just calls a macro defined in
      vg_cachesim_gen.c

vg_cachegen:
    - has been cvs removed as it is no longer needed.

Makefile.am:
    - added vg_cachesim_gen.c

    - removed vg_cachegen

configure.in:
    - removed vg_cachegen


git-svn-id: svn://svn.valgrind.org/valgrind/trunk@400
2002-06-08 13:36:03 +00:00
Nicholas Nethercote
1818ed0e51 vg_symtab2.c:
Discovered sometimes a SLINE stabs entry is the last one (which broke an
    assertion).  In such a case, we must guess the line's instruction address
    range -- I've guessed 4, arbitrarily.

vg_cachegen.in, vg_cachesim_{I1,D1,L2}.c:
    Discovered a bad bug in the cache simulation:  when determining if a
    references straddles two memory blocks, to find the end of the range I was
    adding 'size' to the base address, rather than 'size - 1'.  This was
    causing way too many straddled references, which would inflate the miss
    counts.

vg_cachesim.c:
    Minor stuff


git-svn-id: svn://svn.valgrind.org/valgrind/trunk@176
2002-04-30 13:44:01 +00:00
Nicholas Nethercote
fcc45a9e85 New files:
- vg_cachesim.c
  - vg_cachesim_{I1,D1,L2}.c
  - vg_annotate.in
  - vg_cachegen.in

Changes to existing files:

  - valgrind/valgrind.in, added option:

        --cachesim=no|yes       [no]

  - Makefile/Makefile.am:
        * added vg_cachesim.c to valgrind_so_SOURCES var
        * added vg_cachesim_I1.c, vg_cachesim_D1.c, vg_cachesim_L2.c to
          noinst_HEADERS var
        * added vg_annotate, vg_cachegen to 'bin_SCRIPTS' var, and added empty
          targets for them

  - vg_main.c:
        * added two offsets for cache sim functions (put in positions 17a,17b)
        * added option handling (detection of --cachesim=yes which turns off of
          --instrument);
        * added calls to cachesim initialisation/finalisation functions

  - vg_mylibc: added some system call wrappers (for chmod, open_write, etc) for
    file writing

  - vg_symtab2.c:
        * allow it to read symbols if either of --instrument or --cachesim is
          used
        * made vg_symtab2.c:vg_what_{line,fn}_is_this extern, renaming it as
          VG_(what_line_is_this) (and added to vg_include.h)
        * completely rewrote the read loop in vg_read_lib_symbols, fixing
          several bugs.  Much better now, although probably not perfect.  It's
          also relatively fragile -- I'm using the "die immediately if anything
          unexpected happens" approach.

  - vg_to_ucode.c:
        * in VG_(disBB), patching in x86 instruction size into extra4b field of
          JMP instructions at the end of basic blocks if --cachesim=yes.
          Shifted things around to do this;  also had to fiddle around with
          single-step stuff to get this to work, by not sticking extra JMPs on
          the end of the single-instruction block if there was already one
          there (to avoid breaking an assertion in vg_cachesim.c).  Did a
          similar thing to avoid an extra JMP on huge basic blocks that are
          split.

  - vg_translate.c:
        * if --cachesim=yes call the cachesim instrumentation phase
        * made some functions extern and renamed:
                allocCodeBlock() --> VG_(allocCodeBlock)()
                freeCodeBlock()  --> VG_(freeCodeBlock)()
                copyUInstr()     --> VG_(copyUInstr)()
          (added to vg_include.h too)

  - vg_include.c: declared
        * cachesim offsets
        * exports of vg_cachesim.c
        * added four new profiling events (increasing VGP_M_CCS to 24 -- I kept
          the spare ones)
        * added comment about UInstr.extra4b field being used for instr size in
          JMPs for cache simulation

  - docs/manual.html:
        * Added --cachesim option to section 2.5.
        * Added cache profiling stuff as section 7.


git-svn-id: svn://svn.valgrind.org/valgrind/trunk@168
2002-04-29 16:03:24 +00:00