to support profiling. It is the responsibility of front ends (toIR.c)
to generate these. For each instruction, the first IR stmt emitted
should be an IMark, stating the guest address and length of the guest
instruction represented by the IR that follows. All IR stmts
following the IMark but before the next IMark are then assumed to
'belong to' the guest insn described by the first IMark. IMarks do
not denote executable code and can be ignored at any point in the
proceedings; they are an optional addition which help
profiling-annotators to navigate the IR stmt stream.
This commit adds IR level infrastructure for IMarks and IMark
generation in the x86 front end. The amd64 and ppc32 front end are
not yet done.
git-svn-id: svn://svn.valgrind.org/vex/trunk@1046
since eventually users of the library will refer to them, and unless
they exist in all guest states, compilation failure will result.
These fields contain the size and length of an area of icache
invalidated by any icache-flushing instruction encountered. On x86
and amd64 there is no such insn and so they are zeroed at startup and
play no further role at all. But on ppc32 they are written to as a
result of executing an 'icbi' instruction.
git-svn-id: svn://svn.valgrind.org/vex/trunk@1043
Consolidated spr (non-gpr/fpr) register interface
Brought together separate guest XER flags to single word
+ fixed up switchback (latter slighly broken since r1002)
Few more comments, vasserts etc.
Updated page refs to PPC32 docs
git-svn-id: svn://svn.valgrind.org/vex/trunk@1006
primops operating on it. Use this to implement amd64 64x64->128
multiplies (will also be useful for divides).
git-svn-id: svn://svn.valgrind.org/vex/trunk@870
to make it clear they operate on 128-bit *vector* values. This is so
as to facilitate introduction of a 128-bit *scalar* type into IR
without causing confusion.
git-svn-id: svn://svn.valgrind.org/vex/trunk@867
- Filled out the helper functions for xer_ov,ca
- Added some DIPs
- Using storeBE(),loadBE instead of LE
TODO: Need to set up the IR for this!
git-svn-id: svn://svn.valgrind.org/vex/trunk@765
Added some clean helper functions to calculate CR0 and XER flags
Made a start on add and branch ops (mostly to get a feel, will prob have
to redo)
git-svn-id: svn://svn.valgrind.org/vex/trunk@755
made, record precisely the areas of guest address space from which the
translation was made. This is needed to be sure we can later discard
translations accurately. The new info is record in a structure called
VexGuestExtents.
git-svn-id: svn://svn.valgrind.org/vex/trunk@720
to bring them into line with how SSE works. Previously, MMX was done
using helper functions calls inserted by the front end. This meant
proper MMX instrumentation was impossible (unlike SSE). Now it works
the way all other code does: the front end does not insert calls to
helper functions, but rather builds expression trees using 64-bit
vector primops. These are instrumented as the 128-bit vector primops
already are, and passed to the back ends.
Because emitting combined x87 and MMX code together is too complex,
the x86 back end generates calls to the same helpers as before --
except they are invisible to the front end. And, of course, some of
those calls may now be running instrumentation operations rather than
real-value operations.
git-svn-id: svn://svn.valgrind.org/vex/trunk@712
* x86 guest: fix longstanding bug in fsave/frstor -- they dumped
FP registers in physical order, instead of ST order
* x86 guest: implement fxsave
git-svn-id: svn://svn.valgrind.org/vex/trunk@694
Supported x86 subarchitectures:
* sse0 - have fxsave/fxrstor (ie, the SSE state), but no sse insns
That is, Pentium II and later
* sse1 - have SSE1 - Pentium III and later
* sse2 - have SSE2 - Pentium 4 and M and later
git-svn-id: svn://svn.valgrind.org/vex/trunk@678
