Commit Graph

10 Commits

Author SHA1 Message Date
Julian Seward
ea1f136cd7 Print useful diagnostics if reg-alloc bombs due to bogus live ranges
in the input code.


git-svn-id: svn://svn.valgrind.org/vex/trunk@877
2005-02-09 19:13:29 +00:00
Julian Seward
d21448887c Rename some variables and types, to make it easier to read. No
functionality changes.



git-svn-id: svn://svn.valgrind.org/vex/trunk@685
2004-12-30 01:44:51 +00:00
Julian Seward
39789516fc Remove register preferencing mechanism; does not seem to help.
git-svn-id: svn://svn.valgrind.org/vex/trunk@684
2004-12-30 00:14:54 +00:00
Julian Seward
62b1fa8079 x86 host: Stuff in support of memchecking of 64x2 vector FP.
git-svn-id: svn://svn.valgrind.org/vex/trunk@647
2004-12-10 21:45:38 +00:00
Julian Seward
6851682a46 x86 host: make a start on SSE code generation.
git-svn-id: svn://svn.valgrind.org/vex/trunk@604
2004-12-01 23:19:36 +00:00
Julian Seward
8464fc72e9 In the back end, rename the register classes (in enum HRegClass) more
consistently, in preparation for SSE instruction selection on x86
host.



git-svn-id: svn://svn.valgrind.org/vex/trunk@603
2004-12-01 02:24:44 +00:00
Julian Seward
ecdbfec7f1 Add copyright notices.
git-svn-id: svn://svn.valgrind.org/vex/trunk@548
2004-11-12 17:40:23 +00:00
Julian Seward
8355f0e4b9 Silence compiler warning.
git-svn-id: svn://svn.valgrind.org/vex/trunk@491
2004-11-04 19:43:51 +00:00
Julian Seward
f0edcddd8c Add code to do register preferencing (moves from vreg to rreg cause
the vreg to be preferenced to rreg).  However, this is disabled as it
usually makes things worse.



git-svn-id: svn://svn.valgrind.org/vex/trunk@465
2004-10-30 22:23:53 +00:00
Julian Seward
c5fd5457e1 Add and use a new version of the register allocator, which is simpler
and produces much less spill code around real-reg live ranges
(a.k.a. calls to helper functions)



git-svn-id: svn://svn.valgrind.org/vex/trunk@460
2004-10-30 13:00:55 +00:00