Necessary changes to Valgrind to support MIPS64LE on Linux.
Minor cleanup/style changes embedded in the patch as well.
The change corresponds to r2687 in VEX.
Patch written by Dejan Jevtic and Petar Jovanovic.
More information about this issue:
https://bugs.kde.org/show_bug.cgi?id=313267
git-svn-id: svn://svn.valgrind.org/valgrind/trunk@13292
Callgrind, Cachegrind, and Lackey call
helpers for memory accesses in bunches, to reduce
register save/restore overhead (and merge load/store
within same instruction into a "modify" event).
The calls should not be done within a RMW section
enclosed by LL/SC instructions, as this reduces the
chance of SC to succeed, and can result in hangs.
For Callgrind, this definitly helped MIPS, and was
committed in r13136. Do the same for Cachegrind/Lackey.
git-svn-id: svn://svn.valgrind.org/valgrind/trunk@13143
Because most Ir accesses touch only one line, and this
can be detected at instrumentation time, use a special
handler for that. This handler does not need to check
cache line crossing at runtime.
This does not change the results of the simulator at all,
but improves runtime by around 15% on perf benchmarks.
git-svn-id: svn://svn.valgrind.org/valgrind/trunk@13095
In addition to "__attribute__((always_inline))", gcc wants
"__inline__" to be used, otherwise the warning
warning: always_inline function might not be inlinable
is printed. However, this does not have any effect on
performance (probably "static" makes gcc 4.7 already inlining
the functions?).
git-svn-id: svn://svn.valgrind.org/valgrind/trunk@13092
Update trace cache warning so that it is the same as before the cache reorg
(avoid failure of some tests on Pentium4 as the warning output
must match what is filtered by cachegrind/tests/filter_stderr)
git-svn-id: svn://svn.valgrind.org/valgrind/trunk@13060
New function write_cache_info to dump what was detected for debugging
purposes.
New function cache_info_is_sensible to ensure that autodetected
cache info lives up to the promises made in libvex.h.
Moved the trace-cache related kludgery to cachegrind where it belongs.
git-svn-id: svn://svn.valgrind.org/valgrind/trunk@13053
It's reorg only. No new cache autodetection stuff has been added.
coregrind
pub_tool_cpuid.h is removed as it is no longer exposed to tools.
Its contents has moved to pub_core_cpuid.h.
New file: coregrind/m_cache.c to contain the autodetect code for
cache configurations and define other cache characteristics that
cannot be autodetected (i.e. icaches_maintain_coherence). Most of
cg-arch/x86-amd64.c was moved here. The cache detection code for
x86-64 needs to be fixed to properly initialise VexCacheInfo. It
currently has cachegrind bias.
m_cache.c exports a single function (to coregrind):
VG_(machine_get_cache_info)(VexArchInfo *vai)
This function is called from VG_(machine_get_hwcaps) after hwcaps have
been detected.
cachegrind
Remove cachegrind/cg-{ppc32,ppc43,arm,mips32,s390x,x86-amd64}.c
With the exception of x86/mamd64 those were only establishing a
default cache configuration and that is so small a code snippet that
a separate file is no longer warranted. So, the code was moved to
cg-arch.c. Code was added to extract the relevant info from
x86-amd64.
New function maybe_tweak_LLc which captures the code to massage the
LLc cache configuration into something the simulator can handle. This
was originally in cg-x86-amd64.c but should be used to all architectures.
Changed warning message about missing cache auto-detect feature
to be more useful. Adapted filter-stderr scripts accordingly.
git-svn-id: svn://svn.valgrind.org/valgrind/trunk@13028
This saves instructions in hot path, resulting in
3% improvement on average with perf benchmarks.
git-svn-id: svn://svn.valgrind.org/valgrind/trunk@13025
Makes modifications simpler in the future, and
should result in the same code.
This patch was already discussed some time ago on the
dev mailing list, and did not make a difference on
various architectures.
git-svn-id: svn://svn.valgrind.org/valgrind/trunk@13024
cache, use that instead of the L2 -- bringing the code in synch
with documentation.
Also improve the warning message to be more meaningful.
git-svn-id: svn://svn.valgrind.org/valgrind/trunk@12911
Option sp-at-mem-access can be used by tools which do not
need an up to date BP and IP at each mem access.
It is needed however to have SP up to date at each memory
access, as an up to date SP is needed to grow the stack in
m_signals.c
Tools massif, cachegrind and callgrind are using sp-at-mem-access
as default.
None tool could also use sp-at-mem-access but default is kept
to unwindregs-at-mem-access (similar to memcheck, drd, helgrind, exp-sgcheck).
exp-dhat, exp-bbv, lackey have not been looked at to see if they
could make use of sp-at-mem-access.
Validated on x86, amd64, ppc64 and s390x.
git-svn-id: svn://svn.valgrind.org/valgrind/trunk@12872
cachegrind: use the new function to abort startup if the minumum line
size is smaller than the size of the largest guest register.
Partially derived from a patch by Josef Weidendorfer.
git-svn-id: svn://svn.valgrind.org/valgrind/trunk@12605
in .S files. Also included here is some cleanup, including a reversion
of r10378. Fixes bugzilla #197914.
git-svn-id: svn://svn.valgrind.org/valgrind/trunk@12555
Patch by Philippe Waroquiers, slightly changed.
This actually was a regression from 3.6.1, but the patch
also improves on printed messages, and refactors common
code between cachegrind and callgrind.
git-svn-id: svn://svn.valgrind.org/valgrind/trunk@12013
For a Sandybridge desktop, previously this resulted in
...
--14842-- warning: Unknown Intel cache config value (0x76), ignoring
...
with Cachegrind/Callgrind
git-svn-id: svn://svn.valgrind.org/valgrind/trunk@11811
side components. (Florian Krohm <britzel@acm.org> and Christian
Borntraeger <borntraeger@de.ibm.com>). Fixes#243404.
git-svn-id: svn://svn.valgrind.org/valgrind/trunk@11604
