endianness in VEX).
In short: in m_machine.c, VG_(machine_get_hwcaps), get the endianness
of the host, and pass it through to all places (in VEX) where it is
required.
git-svn-id: svn://svn.valgrind.org/valgrind/trunk@14184
Tests for 64bit FPU instructions on MIPS32 platforms.
Some mips instructions can cause SIGILL (Illegal instruction),
so we need to add SIGILL signal and a proper handler for that signal.
git-svn-id: svn://svn.valgrind.org/valgrind/trunk@13817
only reachable via other thread live register
The exiting thread will have its registers considered as not reachable
anymore, registers of other threads will be considered reachable.
This is ensured by using a different exit reason for the
exiting thread and for the other threads.
git-svn-id: svn://svn.valgrind.org/valgrind/trunk@13670
Bug #326113. This is a bit conservative, but it is what the linux kernel
also seems to be doing. If AVX support is missing (because the OS doesn't
save the wide registers), then also don't report supporting BMI.
git-svn-id: svn://svn.valgrind.org/valgrind/trunk@13656
Follow up to VEX r2764.
Add detection of Cavium in /proc/cpuinfo, and test for DSP ASEs only for
platforms with Company ID == MIPS.
git-svn-id: svn://svn.valgrind.org/valgrind/trunk@13554
Some processors like the AMD Athlon "Classic" support mmxext,
a sse1 subset. This subset is not properly detected by VEX.
The subset uses the same encoding as the sse1 instructions.
The subset is described at:
http://support.amd.com/us/Embedded_TechDocs/22466.pdfhttps://en.wikipedia.org/wiki/3DNow!#3DNow.21_extensions
Detects mmxext subset from cpuid information (and enables it
when full sse1 is found). Also fixes the prereq of
none/tests/x86/insn_mmxext.vgtest so that it also runs when
full sse1 (and not just the mmxext subset) is found.
It already passed on such configurations. With the VEX patch
(r2745) it also passes with just the mmxext subset.
git-svn-id: svn://svn.valgrind.org/valgrind/trunk@13515
The IBM Power ISA 2.07 has been published on power.org, and IBM's new POWER8
processor is under development to implement that ISA. This patch provides
initial runtime and testsuite support for running Valgrind on POWER8 systems
running a soon-to-be released Linux distribution. This Linux distro will
include a POWER8-tuned libc that uses a subset of the new instructions from
ISA 2.07. Since virtually all applications link with libc, it would be
impossible to run an application under Valgrind on this distro without adding
support for these new instructions to Valgrind, so that's the intent of this
patch. Note that applications built on this distro will *not* employ new POWER8
instructions by default. There are roughly 150 new instructions in the Power
ISA 2.07, including hardware transaction management (HTM). Support for these
new instructions (modulo the subset included in this bug) will be added to
Valgrind in a phased approach, similar to what we did for Power ISA 2.06.
Bugzilla 322294, VEX commit 2740
git-svn-id: svn://svn.valgrind.org/valgrind/trunk@13494
Also ignore AT_DCACHEBSIZE entries in the auxiliary vector as they
are not needed.
Fixes BZ 306587.
git-svn-id: svn://svn.valgrind.org/valgrind/trunk@13481
See companion patch VEX r2719.
Patch by Maran Pakkirisamy (maranp@linux.vnet.ibm.com).
Part of fixing BZ #307113
git-svn-id: svn://svn.valgrind.org/valgrind/trunk@13387
Necessary changes to Valgrind to support MIPS64LE on Linux.
Minor cleanup/style changes embedded in the patch as well.
The change corresponds to r2687 in VEX.
Patch written by Dejan Jevtic and Petar Jovanovic.
More information about this issue:
https://bugs.kde.org/show_bug.cgi?id=313267
git-svn-id: svn://svn.valgrind.org/valgrind/trunk@13292
First, use STFLE whenever possible (i.e. for all facilities that
were introduced at the same time STFLE was or later). Turns out,
that is most facilities we're interesting in probing, except long
displacement.
Secondly, remove magic constants denoting facility bits and use
the definition from libvex_s390x_common.h
Thirdly, build up the debugging message that shows the status of
the probed facilities in a generic way so it won't have to be
changed when facilities are added.
git-svn-id: svn://svn.valgrind.org/valgrind/trunk@13174
It's reorg only. No new cache autodetection stuff has been added.
coregrind
pub_tool_cpuid.h is removed as it is no longer exposed to tools.
Its contents has moved to pub_core_cpuid.h.
New file: coregrind/m_cache.c to contain the autodetect code for
cache configurations and define other cache characteristics that
cannot be autodetected (i.e. icaches_maintain_coherence). Most of
cg-arch/x86-amd64.c was moved here. The cache detection code for
x86-64 needs to be fixed to properly initialise VexCacheInfo. It
currently has cachegrind bias.
m_cache.c exports a single function (to coregrind):
VG_(machine_get_cache_info)(VexArchInfo *vai)
This function is called from VG_(machine_get_hwcaps) after hwcaps have
been detected.
cachegrind
Remove cachegrind/cg-{ppc32,ppc43,arm,mips32,s390x,x86-amd64}.c
With the exception of x86/mamd64 those were only establishing a
default cache configuration and that is so small a code snippet that
a separate file is no longer warranted. So, the code was moved to
cg-arch.c. Code was added to extract the relevant info from
x86-amd64.
New function maybe_tweak_LLc which captures the code to massage the
LLc cache configuration into something the simulator can handle. This
was originally in cg-x86-amd64.c but should be used to all architectures.
Changed warning message about missing cache auto-detect feature
to be more useful. Adapted filter-stderr scripts accordingly.
git-svn-id: svn://svn.valgrind.org/valgrind/trunk@13028
cachegrind: use the new function to abort startup if the minumum line
size is smaller than the size of the largest guest register.
Partially derived from a patch by Josef Weidendorfer.
git-svn-id: svn://svn.valgrind.org/valgrind/trunk@12605
a new machine as opposed to a too old machine.
Patch by Christian Borntraeger (borntraeger@de.ibm.com) with additional
commentary. Fixes 298394.
git-svn-id: svn://svn.valgrind.org/valgrind/trunk@12534
VG_(machine_get_hwcaps) for all architectures in pub_core_machine.h
and avoid double maintenance.
git-svn-id: svn://svn.valgrind.org/valgrind/trunk@12532
about leaked or reachable blocks)
This patch implements two new memcheck gdbserver monitor commands:
block_list <loss_record_nr>
after a leak search, shows the list of blocks of <loss_record_nr>
who_points_at <addr> [<len>]
shows places pointing inside <len> (default 1) bytes at <addr>
(with len 1, only shows "start pointers" pointing exactly to <addr>,
with len > 1, will also show "interior pointers")
Compiled and reg-tested on f12/x86, deb5/amd64, f16/ppc64.
The 'block_list' command is implemented on top of the
lr_array/lc_chunks/lc_extras arrays used during the last leak search.
NB: no impact on the memory for the typical Valgrind usage where a leak
search is only done at the end of the run.
Printing the block_list of a loss record simply consists in scanning the
lc_chunks to find back the chunks corresponding to the loss record for which
block lists is requested.
The 'who_points_at' command is implemented by doing a scan similar to
(but simpler than) the leak search scan.
lc_scan_memory has been enhanced to have a mode to search for a specific
address, rather than to search for all allocated blocks.
VG_(apply_to_GP_regs) has been enhanced to also provide the ThreadId and
register name in the callback function.
The patch touches multiple files (but most changes are easy/trivial or factorise
existing code).
Most significant changes are in memcheck/mc_leakcheck.c :
* changed the LC_Extra struct to remember the clique for indirect leaks
(size of structure not changed).
* made lr_array a static global
* changed lc_scan_memory:
to have a search mode for a specific address (for who_points_at)
(for leak search) to pass a 'current clique' in addition to the clique
leader
so as to have a proper clique hierarchy for indirectly leaked blocks.
* print_results: reset values at the beginning of the print_result of the
next leak search, rather than at the end of print_results of the previous
leak search.
This allows to continue showing the same info for loss records till a new
leak search is done.
* new function print_clique which recursively prints a group of leaked
blocks, starting from the clique leader.
* new function MC_(print_block_list) : calls print_clique for each clique
leader found for the given loss record.
* static void scan_memory_root_set : code extracted from
MC_(detect_memory_leaks) (no relevant change)
* void MC_(who_points_at) : calls scan_memory_root_set, lc_scan_memory
and VG_(apply_to_GP_regs)(search_address_in_GP_reg) to search
pointers to the given address.
git-svn-id: svn://svn.valgrind.org/valgrind/trunk@12357
