zenithsiz/ftmemsim-valgrind
1
0
Fork 0
mirror of https://github.com/Zenithsiz/ftmemsim-valgrind.git synced 2026-02-04 02:18:37 +00:00
Code Issues Actions Packages Projects Releases Wiki Activity

mc_LOADVn_slow: also allow --partial-loads-ok=yes to grant an

Browse Source 
exemption for aligned 32 bit loads on 64 bit targets, since it appears
to be necessary.


git-svn-id: svn://svn.valgrind.org/valgrind/trunk@13672
This commit is contained in:
Julian Seward 2013-10-22 15:36:59 +00:00
parent acddb7f8b3
commit e37bfc02f3
1 changed files with 17 additions and 0 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

17
memcheck/mc_main.c
View File

@ -1363,6 +1363,23 @@ ULong mc_LOADVn_slow ( Addr a, SizeT nBits, Bool bigendian )
return vbits64;
}
/* Also, in appears that gcc generates string-stepping code in
32-bit chunks on 64 bit platforms. So, also grant an exception
for this case. Note that the first clause of the conditional
(VG_WORDSIZE == 8) is known at compile time, so the whole clause
will get folded out in 32 bit builds. */
if (VG_WORDSIZE == 8
&& VG_IS_4_ALIGNED(a) && nBits == 32 && n_addrs_bad < 4) {
tl_assert(V_BIT_UNDEFINED == 1 && V_BIT_DEFINED == 0);
/* (really need "UifU" here...)
vbits64 UifU= pessim64 (is pessimised by it, iow) */
vbits64 |= pessim64;
/* Mark the upper 32 bits as undefined, just to be on the safe
side. */
vbits64 |= (((ULong)V_BITS32_UNDEFINED) << 32);
return vbits64;
}
/* Exemption doesn't apply. Flag an addressing error in the normal
way. */
MC_(record_address_error)( VG_(get_running_tid)(), a, szB, False );