mirror of
https://github.com/Zenithsiz/ftmemsim-valgrind.git
synced 2026-02-04 02:18:37 +00:00
Complete CALL_FN_W_* wrappers for amd64-linux.
git-svn-id: svn://svn.valgrind.org/valgrind/trunk@5748
This commit is contained in:
Julian Seward
parent
b74d8afad0
commit
c4a8d96725
@ -919,6 +919,328 @@ typedef
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lval = (__typeof__(lval)) _res; \
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} while (0)
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#define CALL_FN_W_WWW(lval, orig, arg1,arg2,arg3) \
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do { \
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volatile OrigFn _orig = (orig); \
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volatile unsigned long _argvec[4]; \
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volatile unsigned long _res; \
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_argvec[0] = (unsigned long)_orig.nraddr; \
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_argvec[1] = (unsigned long)(arg1); \
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_argvec[2] = (unsigned long)(arg2); \
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_argvec[3] = (unsigned long)(arg3); \
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__asm__ volatile( \
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"movq 24(%%rax), %%rdx\n\t" \
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"movq 16(%%rax), %%rsi\n\t" \
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"movq 8(%%rax), %%rdi\n\t" \
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"movq (%%rax), %%rax\n\t" /* target->%rax */ \
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VALGRIND_CALL_NOREDIR_RAX \
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: /*out*/ "=a" (_res) \
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: /*in*/ "a" (&_argvec[0]) \
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: /*trash*/ "cc", "memory", __CALLER_SAVED_REGS \
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); \
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lval = (__typeof__(lval)) _res; \
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} while (0)
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#define CALL_FN_W_WWWW(lval, orig, arg1,arg2,arg3,arg4) \
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do { \
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volatile OrigFn _orig = (orig); \
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volatile unsigned long _argvec[5]; \
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volatile unsigned long _res; \
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_argvec[0] = (unsigned long)_orig.nraddr; \
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_argvec[1] = (unsigned long)(arg1); \
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_argvec[2] = (unsigned long)(arg2); \
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_argvec[3] = (unsigned long)(arg3); \
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_argvec[4] = (unsigned long)(arg4); \
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__asm__ volatile( \
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"movq 32(%%rax), %%rcx\n\t" \
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"movq 24(%%rax), %%rdx\n\t" \
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"movq 16(%%rax), %%rsi\n\t" \
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"movq 8(%%rax), %%rdi\n\t" \
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"movq (%%rax), %%rax\n\t" /* target->%rax */ \
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VALGRIND_CALL_NOREDIR_RAX \
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: /*out*/ "=a" (_res) \
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: /*in*/ "a" (&_argvec[0]) \
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: /*trash*/ "cc", "memory", __CALLER_SAVED_REGS \
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); \
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lval = (__typeof__(lval)) _res; \
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} while (0)
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#define CALL_FN_W_5W(lval, orig, arg1,arg2,arg3,arg4,arg5) \
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do { \
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volatile OrigFn _orig = (orig); \
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volatile unsigned long _argvec[6]; \
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volatile unsigned long _res; \
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_argvec[0] = (unsigned long)_orig.nraddr; \
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_argvec[1] = (unsigned long)(arg1); \
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_argvec[2] = (unsigned long)(arg2); \
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_argvec[3] = (unsigned long)(arg3); \
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_argvec[4] = (unsigned long)(arg4); \
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_argvec[5] = (unsigned long)(arg5); \
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__asm__ volatile( \
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"movq 40(%%rax), %%r8\n\t" \
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"movq 32(%%rax), %%rcx\n\t" \
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"movq 24(%%rax), %%rdx\n\t" \
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"movq 16(%%rax), %%rsi\n\t" \
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"movq 8(%%rax), %%rdi\n\t" \
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"movq (%%rax), %%rax\n\t" /* target->%rax */ \
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VALGRIND_CALL_NOREDIR_RAX \
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: /*out*/ "=a" (_res) \
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: /*in*/ "a" (&_argvec[0]) \
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: /*trash*/ "cc", "memory", __CALLER_SAVED_REGS \
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); \
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lval = (__typeof__(lval)) _res; \
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} while (0)
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#define CALL_FN_W_6W(lval, orig, arg1,arg2,arg3,arg4,arg5,arg6) \
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do { \
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volatile OrigFn _orig = (orig); \
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volatile unsigned long _argvec[7]; \
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volatile unsigned long _res; \
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_argvec[0] = (unsigned long)_orig.nraddr; \
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_argvec[1] = (unsigned long)(arg1); \
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_argvec[2] = (unsigned long)(arg2); \
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_argvec[3] = (unsigned long)(arg3); \
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_argvec[4] = (unsigned long)(arg4); \
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_argvec[5] = (unsigned long)(arg5); \
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_argvec[6] = (unsigned long)(arg6); \
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__asm__ volatile( \
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"movq 48(%%rax), %%r9\n\t" \
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"movq 40(%%rax), %%r8\n\t" \
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"movq 32(%%rax), %%rcx\n\t" \
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"movq 24(%%rax), %%rdx\n\t" \
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"movq 16(%%rax), %%rsi\n\t" \
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"movq 8(%%rax), %%rdi\n\t" \
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"movq (%%rax), %%rax\n\t" /* target->%rax */ \
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VALGRIND_CALL_NOREDIR_RAX \
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: /*out*/ "=a" (_res) \
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: /*in*/ "a" (&_argvec[0]) \
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: /*trash*/ "cc", "memory", __CALLER_SAVED_REGS \
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); \
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lval = (__typeof__(lval)) _res; \
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} while (0)
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#define CALL_FN_W_7W(lval, orig, arg1,arg2,arg3,arg4,arg5,arg6, \
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arg7) \
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do { \
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volatile OrigFn _orig = (orig); \
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volatile unsigned long _argvec[8]; \
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volatile unsigned long _res; \
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_argvec[0] = (unsigned long)_orig.nraddr; \
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_argvec[1] = (unsigned long)(arg1); \
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_argvec[2] = (unsigned long)(arg2); \
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_argvec[3] = (unsigned long)(arg3); \
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_argvec[4] = (unsigned long)(arg4); \
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_argvec[5] = (unsigned long)(arg5); \
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_argvec[6] = (unsigned long)(arg6); \
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_argvec[7] = (unsigned long)(arg7); \
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__asm__ volatile( \
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"pushq 56(%%rax)\n\t" \
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"movq 48(%%rax), %%r9\n\t" \
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"movq 40(%%rax), %%r8\n\t" \
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"movq 32(%%rax), %%rcx\n\t" \
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"movq 24(%%rax), %%rdx\n\t" \
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"movq 16(%%rax), %%rsi\n\t" \
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"movq 8(%%rax), %%rdi\n\t" \
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"movq (%%rax), %%rax\n\t" /* target->%rax */ \
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VALGRIND_CALL_NOREDIR_RAX \
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"addq $8, %%rsp\n" \
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: /*out*/ "=a" (_res) \
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: /*in*/ "a" (&_argvec[0]) \
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: /*trash*/ "cc", "memory", __CALLER_SAVED_REGS \
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); \
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lval = (__typeof__(lval)) _res; \
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} while (0)
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#define CALL_FN_W_8W(lval, orig, arg1,arg2,arg3,arg4,arg5,arg6, \
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arg7,arg8) \
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do { \
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volatile OrigFn _orig = (orig); \
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volatile unsigned long _argvec[9]; \
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volatile unsigned long _res; \
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_argvec[0] = (unsigned long)_orig.nraddr; \
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_argvec[1] = (unsigned long)(arg1); \
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_argvec[2] = (unsigned long)(arg2); \
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_argvec[3] = (unsigned long)(arg3); \
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_argvec[4] = (unsigned long)(arg4); \
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_argvec[5] = (unsigned long)(arg5); \
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_argvec[6] = (unsigned long)(arg6); \
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_argvec[7] = (unsigned long)(arg7); \
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_argvec[8] = (unsigned long)(arg8); \
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__asm__ volatile( \
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"pushq 64(%%rax)\n\t" \
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"pushq 56(%%rax)\n\t" \
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"movq 48(%%rax), %%r9\n\t" \
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"movq 40(%%rax), %%r8\n\t" \
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"movq 32(%%rax), %%rcx\n\t" \
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"movq 24(%%rax), %%rdx\n\t" \
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"movq 16(%%rax), %%rsi\n\t" \
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"movq 8(%%rax), %%rdi\n\t" \
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"movq (%%rax), %%rax\n\t" /* target->%rax */ \
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VALGRIND_CALL_NOREDIR_RAX \
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"addq $16, %%rsp\n" \
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: /*out*/ "=a" (_res) \
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: /*in*/ "a" (&_argvec[0]) \
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: /*trash*/ "cc", "memory", __CALLER_SAVED_REGS \
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); \
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lval = (__typeof__(lval)) _res; \
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} while (0)
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#define CALL_FN_W_9W(lval, orig, arg1,arg2,arg3,arg4,arg5,arg6, \
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arg7,arg8,arg9) \
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do { \
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volatile OrigFn _orig = (orig); \
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volatile unsigned long _argvec[10]; \
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volatile unsigned long _res; \
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_argvec[0] = (unsigned long)_orig.nraddr; \
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_argvec[1] = (unsigned long)(arg1); \
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_argvec[2] = (unsigned long)(arg2); \
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_argvec[3] = (unsigned long)(arg3); \
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_argvec[4] = (unsigned long)(arg4); \
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_argvec[5] = (unsigned long)(arg5); \
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_argvec[6] = (unsigned long)(arg6); \
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_argvec[7] = (unsigned long)(arg7); \
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_argvec[8] = (unsigned long)(arg8); \
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_argvec[9] = (unsigned long)(arg9); \
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__asm__ volatile( \
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"pushq 72(%%rax)\n\t" \
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"pushq 64(%%rax)\n\t" \
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"pushq 56(%%rax)\n\t" \
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"movq 48(%%rax), %%r9\n\t" \
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"movq 40(%%rax), %%r8\n\t" \
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"movq 32(%%rax), %%rcx\n\t" \
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"movq 24(%%rax), %%rdx\n\t" \
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"movq 16(%%rax), %%rsi\n\t" \
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"movq 8(%%rax), %%rdi\n\t" \
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"movq (%%rax), %%rax\n\t" /* target->%rax */ \
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VALGRIND_CALL_NOREDIR_RAX \
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"addq $24, %%rsp\n" \
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: /*out*/ "=a" (_res) \
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: /*in*/ "a" (&_argvec[0]) \
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: /*trash*/ "cc", "memory", __CALLER_SAVED_REGS \
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); \
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lval = (__typeof__(lval)) _res; \
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} while (0)
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#define CALL_FN_W_10W(lval, orig, arg1,arg2,arg3,arg4,arg5,arg6, \
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arg7,arg8,arg9,arg10) \
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do { \
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volatile OrigFn _orig = (orig); \
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volatile unsigned long _argvec[11]; \
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volatile unsigned long _res; \
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_argvec[0] = (unsigned long)_orig.nraddr; \
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_argvec[1] = (unsigned long)(arg1); \
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_argvec[2] = (unsigned long)(arg2); \
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_argvec[3] = (unsigned long)(arg3); \
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_argvec[4] = (unsigned long)(arg4); \
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_argvec[5] = (unsigned long)(arg5); \
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_argvec[6] = (unsigned long)(arg6); \
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_argvec[7] = (unsigned long)(arg7); \
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_argvec[8] = (unsigned long)(arg8); \
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_argvec[9] = (unsigned long)(arg9); \
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_argvec[10] = (unsigned long)(arg10); \
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__asm__ volatile( \
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"pushq 80(%%rax)\n\t" \
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"pushq 72(%%rax)\n\t" \
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"pushq 64(%%rax)\n\t" \
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"pushq 56(%%rax)\n\t" \
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"movq 48(%%rax), %%r9\n\t" \
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"movq 40(%%rax), %%r8\n\t" \
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"movq 32(%%rax), %%rcx\n\t" \
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"movq 24(%%rax), %%rdx\n\t" \
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"movq 16(%%rax), %%rsi\n\t" \
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"movq 8(%%rax), %%rdi\n\t" \
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"movq (%%rax), %%rax\n\t" /* target->%rax */ \
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VALGRIND_CALL_NOREDIR_RAX \
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"addq $32, %%rsp\n" \
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: /*out*/ "=a" (_res) \
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: /*in*/ "a" (&_argvec[0]) \
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: /*trash*/ "cc", "memory", __CALLER_SAVED_REGS \
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); \
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lval = (__typeof__(lval)) _res; \
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} while (0)
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#define CALL_FN_W_11W(lval, orig, arg1,arg2,arg3,arg4,arg5,arg6, \
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arg7,arg8,arg9,arg10,arg11) \
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do { \
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volatile OrigFn _orig = (orig); \
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volatile unsigned long _argvec[12]; \
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volatile unsigned long _res; \
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_argvec[0] = (unsigned long)_orig.nraddr; \
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_argvec[1] = (unsigned long)(arg1); \
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_argvec[2] = (unsigned long)(arg2); \
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_argvec[3] = (unsigned long)(arg3); \
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_argvec[4] = (unsigned long)(arg4); \
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_argvec[5] = (unsigned long)(arg5); \
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_argvec[6] = (unsigned long)(arg6); \
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_argvec[7] = (unsigned long)(arg7); \
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_argvec[8] = (unsigned long)(arg8); \
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_argvec[9] = (unsigned long)(arg9); \
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_argvec[10] = (unsigned long)(arg10); \
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_argvec[11] = (unsigned long)(arg11); \
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__asm__ volatile( \
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"pushq 88(%%rax)\n\t" \
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"pushq 80(%%rax)\n\t" \
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"pushq 72(%%rax)\n\t" \
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"pushq 64(%%rax)\n\t" \
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"pushq 56(%%rax)\n\t" \
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"movq 48(%%rax), %%r9\n\t" \
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"movq 40(%%rax), %%r8\n\t" \
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"movq 32(%%rax), %%rcx\n\t" \
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"movq 24(%%rax), %%rdx\n\t" \
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"movq 16(%%rax), %%rsi\n\t" \
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"movq 8(%%rax), %%rdi\n\t" \
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"movq (%%rax), %%rax\n\t" /* target->%rax */ \
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VALGRIND_CALL_NOREDIR_RAX \
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"addq $40, %%rsp\n" \
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: /*out*/ "=a" (_res) \
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: /*in*/ "a" (&_argvec[0]) \
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: /*trash*/ "cc", "memory", __CALLER_SAVED_REGS \
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); \
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lval = (__typeof__(lval)) _res; \
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} while (0)
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#define CALL_FN_W_12W(lval, orig, arg1,arg2,arg3,arg4,arg5,arg6, \
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arg7,arg8,arg9,arg10,arg11,arg12) \
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do { \
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volatile OrigFn _orig = (orig); \
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volatile unsigned long _argvec[13]; \
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volatile unsigned long _res; \
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_argvec[0] = (unsigned long)_orig.nraddr; \
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_argvec[1] = (unsigned long)(arg1); \
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_argvec[2] = (unsigned long)(arg2); \
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_argvec[3] = (unsigned long)(arg3); \
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_argvec[4] = (unsigned long)(arg4); \
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_argvec[5] = (unsigned long)(arg5); \
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_argvec[6] = (unsigned long)(arg6); \
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_argvec[7] = (unsigned long)(arg7); \
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_argvec[8] = (unsigned long)(arg8); \
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_argvec[9] = (unsigned long)(arg9); \
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_argvec[10] = (unsigned long)(arg10); \
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_argvec[11] = (unsigned long)(arg11); \
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_argvec[12] = (unsigned long)(arg12); \
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__asm__ volatile( \
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"pushq 96(%%rax)\n\t" \
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"pushq 88(%%rax)\n\t" \
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"pushq 80(%%rax)\n\t" \
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"pushq 72(%%rax)\n\t" \
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"pushq 64(%%rax)\n\t" \
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"pushq 56(%%rax)\n\t" \
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"movq 48(%%rax), %%r9\n\t" \
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"movq 40(%%rax), %%r8\n\t" \
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"movq 32(%%rax), %%rcx\n\t" \
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"movq 24(%%rax), %%rdx\n\t" \
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"movq 16(%%rax), %%rsi\n\t" \
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"movq 8(%%rax), %%rdi\n\t" \
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"movq (%%rax), %%rax\n\t" /* target->%rax */ \
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VALGRIND_CALL_NOREDIR_RAX \
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"addq $48, %%rsp\n" \
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: /*out*/ "=a" (_res) \
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: /*in*/ "a" (&_argvec[0]) \
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: /*trash*/ "cc", "memory", __CALLER_SAVED_REGS \
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); \
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lval = (__typeof__(lval)) _res; \
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} while (0)
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#endif /* ARCH_amd64 */
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/* --------------------------- ppc32 --------------------------- */
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