mirror of
https://github.com/Zenithsiz/ftmemsim-valgrind.git
synced 2026-02-04 02:18:37 +00:00
Add ppc host-side isel and instruction support for IROps added in previous commit.
VEX/priv/host_ppc_defs.c, VEX/priv/host_ppc_defs.h:
Dont emit cnttz{w,d}. We may need them on a target which doesn't support
them. Instead we can generate a fairly reasonable alternative sequence with
cntlz{w,d} instead.
Add support for emitting popcnt{w,d}.
VEX/priv/host_ppc_isel.c
Add support for: Iop_ClzNat32 Iop_ClzNat64
Redo support for: Iop_Ctz{32,64} and their Nat equivalents, so as to not use
cnttz{w,d}, as mentioned above.
Add support for: Iop_PopCount64 Iop_PopCount32 Iop_Reverse8sIn32_x1
This commit is contained in:
Julian Seward
parent
4271989815
commit
97d336b79e
@ -501,9 +501,9 @@ const HChar* showPPCUnaryOp ( PPCUnaryOp op ) {
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case Pun_NEG: return "neg";
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case Pun_CLZ32: return "cntlzw";
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case Pun_CLZ64: return "cntlzd";
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case Pun_CTZ32: return "cnttzw";
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case Pun_CTZ64: return "cnttzd";
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case Pun_EXTSW: return "extsw";
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case Pun_POP32: return "popcntw";
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case Pun_POP64: return "popcntd";
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default: vpanic("showPPCUnaryOp");
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}
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}
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@ -4265,20 +4265,19 @@ Int emit_PPCInstr ( /*MB_MOD*/Bool* is_profInc,
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vassert(mode64);
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p = mkFormX(p, 31, r_src, r_dst, 0, 58, 0, endness_host);
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break;
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case Pun_CTZ32: // cnttzw r_dst, r_src
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/* Note oder of src and dst is backwards from normal */
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p = mkFormX(p, 31, r_src, r_dst, 0, 538, 0, endness_host);
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break;
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case Pun_CTZ64: // cnttzd r_dst, r_src
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/* Note oder of src and dst is backwards from normal */
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vassert(mode64);
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p = mkFormX(p, 31, r_src, r_dst, 0, 570, 0, endness_host);
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break;
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case Pun_EXTSW: // extsw r_dst, r_src
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vassert(mode64);
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p = mkFormX(p, 31, r_src, r_dst, 0, 986, 0, endness_host);
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break;
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default: goto bad;
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case Pun_POP32: // popcntw r_dst, r_src
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p = mkFormX(p, 31, r_src, r_dst, 0, 378, 0, endness_host);
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break;
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case Pun_POP64: // popcntd r_dst, r_src
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vassert(mode64);
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p = mkFormX(p, 31, r_src, r_dst, 0, 506, 0, endness_host);
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break;
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default:
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goto bad;
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}
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goto done;
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}
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@ -291,9 +291,9 @@ typedef
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Pun_NOT,
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Pun_CLZ32,
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Pun_CLZ64,
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Pun_CTZ32,
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Pun_CTZ64,
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Pun_EXTSW
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Pun_EXTSW,
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Pun_POP32, // popcntw
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Pun_POP64 // popcntd
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}
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PPCUnaryOp;
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@ -2065,12 +2065,15 @@ static HReg iselWordExpr_R_wrk ( ISelEnv* env, const IRExpr* e,
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return r_dst;
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}
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break;
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case Iop_Clz32:
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case Iop_Clz64: {
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case Iop_Clz32: case Iop_ClzNat32:
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case Iop_Clz64: case Iop_ClzNat64: {
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// cntlz is available even in the most basic (earliest) ppc
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// variants, so it's safe to generate it unconditionally.
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HReg r_src, r_dst;
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PPCUnaryOp op_clz = (op_unop == Iop_Clz32) ? Pun_CLZ32 :
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Pun_CLZ64;
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if (op_unop == Iop_Clz64 && !mode64)
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PPCUnaryOp op_clz = (op_unop == Iop_Clz32 || op_unop == Iop_ClzNat32)
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? Pun_CLZ32 : Pun_CLZ64;
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if ((op_unop == Iop_Clz64 || op_unop == Iop_ClzNat64) && !mode64)
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goto irreducible;
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/* Count leading zeroes. */
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r_dst = newVRegI(env);
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@ -2079,18 +2082,133 @@ static HReg iselWordExpr_R_wrk ( ISelEnv* env, const IRExpr* e,
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return r_dst;
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}
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case Iop_Ctz32:
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case Iop_Ctz64: {
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HReg r_src, r_dst;
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PPCUnaryOp op_clz = (op_unop == Iop_Ctz32) ? Pun_CTZ32 :
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Pun_CTZ64;
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if (op_unop == Iop_Ctz64 && !mode64)
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goto irreducible;
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/* Count trailing zeroes. */
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r_dst = newVRegI(env);
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r_src = iselWordExpr_R(env, e->Iex.Unop.arg, IEndianess);
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addInstr(env, PPCInstr_Unary(op_clz,r_dst,r_src));
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return r_dst;
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//case Iop_Ctz32:
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case Iop_CtzNat32:
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//case Iop_Ctz64:
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case Iop_CtzNat64:
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{
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// Generate code using Clz, because we can't assume the host has
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// Ctz. In particular, part of the fix for bug 386945 involves
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// creating a Ctz in ir_opt.c from smaller fragments.
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PPCUnaryOp op_clz = Pun_CLZ64;
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Int WS = 64;
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if (op_unop == Iop_Ctz32 || op_unop == Iop_CtzNat32) {
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op_clz = Pun_CLZ32;
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WS = 32;
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}
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/* Compute ctz(arg) = wordsize - clz(~arg & (arg - 1)), thusly:
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t1 = arg - 1
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t2 = not arg
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t2 = t2 & t1
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t2 = clz t2
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t1 = WS
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t2 = t1 - t2
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// result in t2
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*/
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HReg arg = iselWordExpr_R(env, e->Iex.Unop.arg, IEndianess);
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HReg t1 = newVRegI(env);
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HReg t2 = newVRegI(env);
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addInstr(env, PPCInstr_Alu(Palu_SUB, t1, arg, PPCRH_Imm(True, 1)));
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addInstr(env, PPCInstr_Unary(Pun_NOT, t2, arg));
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addInstr(env, PPCInstr_Alu(Palu_AND, t2, t2, PPCRH_Reg(t1)));
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addInstr(env, PPCInstr_Unary(op_clz, t2, t2));
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addInstr(env, PPCInstr_LI(t1, WS, False/*!64-bit imm*/));
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addInstr(env, PPCInstr_Alu(Palu_SUB, t2, t1, PPCRH_Reg(t2)));
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return t2;
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}
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case Iop_PopCount64: {
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// popcnt{x,d} is only available in later arch revs (ISA 3.0,
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// maybe) so it's not really correct to emit it here without a caps
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// check for the host.
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if (mode64) {
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HReg r_dst = newVRegI(env);
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HReg r_src = iselWordExpr_R(env, e->Iex.Unop.arg, IEndianess);
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addInstr(env, PPCInstr_Unary(Pun_POP64, r_dst, r_src));
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return r_dst;
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}
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// We don't expect to be required to handle this in 32-bit mode.
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break;
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}
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case Iop_PopCount32: {
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// Similar comment as for Ctz just above applies -- we really
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// should have a caps check here.
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HReg r_dst = newVRegI(env);
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// This actually generates popcntw, which in 64 bit mode does a
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// 32-bit count individually for both low and high halves of the
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// word. Per the comment at the top of iselIntExpr_R, in the 64
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// bit mode case, the user of this result is required to ignore
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// the upper 32 bits of the result. In 32 bit mode this is all
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// moot. It is however unclear from the PowerISA 3.0 docs that
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// the instruction exists in 32 bit mode; however our own front
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// end (guest_ppc_toIR.c) accepts it, so I guess it does exist.
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HReg r_src = iselWordExpr_R(env, e->Iex.Unop.arg, IEndianess);
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addInstr(env, PPCInstr_Unary(Pun_POP32, r_dst, r_src));
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return r_dst;
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}
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case Iop_Reverse8sIn32_x1: {
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// A bit of a mouthful, but simply .. 32-bit byte swap.
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// This is pretty rubbish code. We could do vastly better if
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// rotates, and better, rotate-inserts, were allowed. Note that
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// even on a 64 bit target, the right shifts must be done as 32-bit
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// so as to introduce zero bits in the right places. So it seems
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// simplest to do the whole sequence in 32-bit insns.
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/*
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r = <argument> // working temporary, initial byte order ABCD
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Mask = 00FF00FF
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nMask = not Mask
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tHi = and r, Mask
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tHi = shl tHi, 8
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tLo = and r, nMask
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tLo = shr tLo, 8
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r = or tHi, tLo // now r has order BADC
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and repeat for 16 bit chunks ..
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Mask = 0000FFFF
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nMask = not Mask
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tHi = and r, Mask
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tHi = shl tHi, 16
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tLo = and r, nMask
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tLo = shr tLo, 16
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r = or tHi, tLo // now r has order DCBA
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*/
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HReg r_src = iselWordExpr_R(env, e->Iex.Unop.arg, IEndianess);
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HReg rr = newVRegI(env);
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HReg rMask = newVRegI(env);
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HReg rnMask = newVRegI(env);
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HReg rtHi = newVRegI(env);
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HReg rtLo = newVRegI(env);
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// Copy r_src since we need to modify it
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addInstr(env, mk_iMOVds_RR(rr, r_src));
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// Swap within 16-bit lanes
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addInstr(env, PPCInstr_LI(rMask, 0x00FF00FFULL,
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False/* !64bit imm*/));
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addInstr(env, PPCInstr_Unary(Pun_NOT, rnMask, rMask));
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addInstr(env, PPCInstr_Alu(Palu_AND, rtHi, rr, PPCRH_Reg(rMask)));
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addInstr(env, PPCInstr_Shft(Pshft_SHL, True/*32 bit shift*/,
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rtHi, rtHi,
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PPCRH_Imm(False/*!signed imm*/, 8)));
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addInstr(env, PPCInstr_Alu(Palu_AND, rtLo, rr, PPCRH_Reg(rnMask)));
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addInstr(env, PPCInstr_Shft(Pshft_SHR, True/*32 bit shift*/,
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rtLo, rtLo,
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PPCRH_Imm(False/*!signed imm*/, 8)));
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addInstr(env, PPCInstr_Alu(Palu_OR, rr, rtHi, PPCRH_Reg(rtLo)));
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// And now swap the two 16-bit chunks
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addInstr(env, PPCInstr_LI(rMask, 0x0000FFFFULL,
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False/* !64bit imm*/));
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addInstr(env, PPCInstr_Unary(Pun_NOT, rnMask, rMask));
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addInstr(env, PPCInstr_Alu(Palu_AND, rtHi, rr, PPCRH_Reg(rMask)));
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addInstr(env, PPCInstr_Shft(Pshft_SHL, True/*32 bit shift*/,
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rtHi, rtHi,
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PPCRH_Imm(False/*!signed imm*/, 16)));
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addInstr(env, PPCInstr_Alu(Palu_AND, rtLo, rr, PPCRH_Reg(rnMask)));
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addInstr(env, PPCInstr_Shft(Pshft_SHR, True/*32 bit shift*/,
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rtLo, rtLo,
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PPCRH_Imm(False/*!signed imm*/, 16)));
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addInstr(env, PPCInstr_Alu(Palu_OR, rr, rtHi, PPCRH_Reg(rtLo)));
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return rr;
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}
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case Iop_Left8:
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