mirror of
https://github.com/Zenithsiz/ftmemsim-valgrind.git
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mips: code refactoring (NFC)
Code in VEX/priv/guest_mips_toIR.c is notably refactored. DSP ASE dissasembly has been put in a separate file: guest_mipsdsp_toIR.c. Patch by Aleksandar Rikalo.
This commit is contained in:
Petar Jovanovic
parent
8ed9b61432
commit
92ecddd13e
@ -47,6 +47,7 @@ noinst_HEADERS = \
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priv/guest_arm64_defs.h \
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priv/guest_s390_defs.h \
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priv/guest_mips_defs.h \
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priv/mips_defs.h \
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priv/host_generic_regs.h \
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priv/host_generic_simd64.h \
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priv/host_generic_simd128.h \
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@ -143,6 +144,7 @@ LIBVEX_SOURCES_COMMON = \
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priv/guest_s390_helpers.c \
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priv/guest_s390_toIR.c \
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priv/guest_mips_helpers.c \
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priv/guest_mipsdsp_toIR.c \
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priv/guest_mips_toIR.c \
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priv/host_generic_regs.c \
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priv/host_generic_simd64.c \
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@ -34,6 +34,7 @@ PRIV_HEADERS = priv/host_x86_defs.h \
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priv/guest_arm_defs.h \
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priv/guest_ppc_defs.h \
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priv/guest_mips_defs.h \
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priv/mips_defs.h \
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priv/s390_disasm.h \
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priv/s390_defs.h \
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priv/ir_match.h \
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@ -82,6 +83,7 @@ LIB_OBJS = priv/ir_defs.o \
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priv/guest_arm64_toIR.o \
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priv/guest_ppc_toIR.o \
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priv/guest_s390_toIR.o \
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priv/guest_mipsdsp_toIR.o \
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priv/guest_mips_toIR.o
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PUB_INCLUDES = -Ipub
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@ -409,6 +411,10 @@ priv/guest_mips_helpers.o: $(ALL_HEADERS) priv/guest_mips_helpers.c
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$(CC) $(CCFLAGS) $(ALL_INCLUDES) -o priv/guest_mips_helpers.o \
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-c priv/guest_mips_helpers.c
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priv/guest_mipsdsp_toIR.o: $(ALL_HEADERS) priv/guest_mipsdsp_toIR.c
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$(CC) $(CCFLAGS) $(ALL_INCLUDES) -o priv/guest_mipsdsp_toIR.o \
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-c priv/guest_mipsdsp_toIR.c
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priv/guest_mips_toIR.o: $(ALL_HEADERS) priv/guest_mips_toIR.c
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$(CC) $(CCFLAGS) $(ALL_INCLUDES) -o priv/guest_mips_toIR.o \
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-c priv/guest_mips_toIR.c
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46569
VEX/priv/guest_mips_toIR.c
Normal file → Executable file
46569
VEX/priv/guest_mips_toIR.c
Normal file → Executable file
File diff suppressed because it is too large
Load Diff
9688
VEX/priv/guest_mipsdsp_toIR.c
Normal file
9688
VEX/priv/guest_mipsdsp_toIR.c
Normal file
File diff suppressed because it is too large
Load Diff
421
VEX/priv/mips_defs.h
Normal file
421
VEX/priv/mips_defs.h
Normal file
@ -0,0 +1,421 @@
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/*---------------------------------------------------------------*/
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/*--- begin mips_defs.h ---*/
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/*---------------------------------------------------------------*/
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/*
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This file is part of Valgrind, a dynamic binary instrumentation
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framework.
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Copyright (C) 2017-2019 RT-RK
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mips-valgrind@rt-rk.com
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This program is free software; you can redistribute it and/or
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modify it under the terms of the GNU General Public License as
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published by the Free Software Foundation; either version 2 of the
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License, or (at your option) any later version.
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This program is distributed in the hope that it will be useful, but
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WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with this program; if not, write to the Free Software
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Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA
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02111-1307, USA.
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The GNU General Public License is contained in the file COPYING.
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*/
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#ifndef __VEX_MIPS_DEFS_H
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#define __VEX_MIPS_DEFS_H
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#include "libvex_basictypes.h"
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#include "libvex_ir.h"
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#include "libvex.h"
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/* MOD: The IRSB* into which we're generating code. */
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extern IRSB *irsb;
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/* Is our guest binary 32 or 64bit? Set at each call to
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disInstr_MIPS below. */
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extern Bool mode64;
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/* Pointer to the guest code area. */
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extern const UChar *guest_code;
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/*------------------------------------------------------------*/
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/*--- DSP to IR function ---*/
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/*------------------------------------------------------------*/
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UInt disDSPInstr_MIPS_WRK ( UInt );
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/*------------------------------------------------------------*/
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/*--- Debugging output ---*/
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/*------------------------------------------------------------*/
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#define DIP(format, args...) \
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if (vex_traceflags & VEX_TRACE_FE) \
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vex_printf(format, ## args)
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/* ------------ MIPS32 DSP ASE(r2) accumulators ------------- */
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extern UInt accumulatorGuestRegOffset( UInt );
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/*------------------------------------------------------------*/
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/*--- Helper bits and pieces for creating IR fragments. ---*/
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/*------------------------------------------------------------*/
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static inline IRExpr *mkU8(UInt i)
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{
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vassert(i < 256);
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return IRExpr_Const(IRConst_U8((UChar) i));
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}
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/* Create an expression node for a 16-bit integer constant. */
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static inline IRExpr *mkU16(UInt i)
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{
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return IRExpr_Const(IRConst_U16(i));
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}
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/* Create an expression node for a 32-bit integer constant. */
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static inline IRExpr *mkU32(UInt i)
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{
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return IRExpr_Const(IRConst_U32(i));
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}
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/* Create an expression node for a 64-bit integer constant. */
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static inline IRExpr *mkU64(ULong i)
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{
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return IRExpr_Const(IRConst_U64(i));
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}
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static inline IRExpr *mkexpr(IRTemp tmp)
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{
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return IRExpr_RdTmp(tmp);
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}
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static inline IRExpr *unop(IROp op, IRExpr * a)
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{
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return IRExpr_Unop(op, a);
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}
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static inline IRExpr *binop(IROp op, IRExpr * a1, IRExpr * a2)
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{
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return IRExpr_Binop(op, a1, a2);
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}
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static inline IRExpr *triop(IROp op, IRExpr * a1, IRExpr * a2, IRExpr * a3)
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{
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return IRExpr_Triop(op, a1, a2, a3);
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}
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static inline IRExpr *qop ( IROp op, IRExpr * a1, IRExpr * a2, IRExpr * a3,
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IRExpr * a4 )
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{
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return IRExpr_Qop(op, a1, a2, a3, a4);
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}
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static inline IRExpr *load(IRType ty, IRExpr * addr)
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{
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IRExpr *load1 = NULL;
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#if defined (_MIPSEL)
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load1 = IRExpr_Load(Iend_LE, ty, addr);
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#elif defined (_MIPSEB)
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load1 = IRExpr_Load(Iend_BE, ty, addr);
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#endif
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return load1;
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}
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/* Add a statement to the list held by "irsb". */
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static inline void stmt(IRStmt * st)
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{
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addStmtToIRSB(irsb, st);
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}
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static inline void assign(IRTemp dst, IRExpr * e)
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{
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stmt(IRStmt_WrTmp(dst, e));
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}
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static inline void store(IRExpr * addr, IRExpr * data)
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{
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#if defined (_MIPSEL)
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stmt(IRStmt_Store(Iend_LE, addr, data));
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#elif defined (_MIPSEB)
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stmt(IRStmt_Store(Iend_BE, addr, data));
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#endif
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}
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/* Generate a new temporary of the given type. */
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static inline IRTemp newTemp(IRType ty)
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{
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vassert(isPlausibleIRType(ty));
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return newIRTemp(irsb->tyenv, ty);
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}
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static inline UShort extend_s_9to16(UInt x)
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{
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return (UShort) ((((Int) x) << 23) >> 23);
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}
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static inline UShort extend_s_10to16(UInt x)
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{
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return (UShort) ((((Int) x) << 22) >> 22);
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}
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static inline UInt extend_s_10to32(UInt x)
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{
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return (UInt)((((Int) x) << 22) >> 22);
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}
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static inline ULong extend_s_10to64(UInt x)
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{
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return (ULong)((((Long) x) << 54) >> 54);
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}
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static inline UInt extend_s_16to32(UInt x)
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{
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return (UInt) ((((Int) x) << 16) >> 16);
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}
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static inline UInt extend_s_18to32(UInt x)
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{
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return (UInt) ((((Int) x) << 14) >> 14);
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}
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static inline UInt extend_s_19to32(UInt x)
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{
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return (UInt) ((((Int) x) << 13) >> 13);
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}
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static inline UInt extend_s_23to32(UInt x)
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{
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return (UInt) ((((Int) x) << 9) >> 9);
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}
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static inline UInt extend_s_26to32(UInt x)
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{
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return (UInt) ((((Int) x) << 6) >> 6);
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}
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static inline ULong extend_s_16to64 ( UInt x )
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{
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return (ULong) ((((Long) x) << 48) >> 48);
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}
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static inline ULong extend_s_18to64 ( UInt x )
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{
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return (ULong) ((((Long) x) << 46) >> 46);
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}
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static inline ULong extend_s_19to64(UInt x)
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{
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return (ULong) ((((Long) x) << 45) >> 45);
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}
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static inline ULong extend_s_23to64(UInt x)
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{
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return (ULong) ((((Long) x) << 41) >> 41);
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}
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static inline ULong extend_s_26to64(UInt x)
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{
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return (ULong) ((((Long) x) << 38) >> 38);
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}
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static inline ULong extend_s_32to64 ( UInt x )
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{
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return (ULong) ((((Long) x) << 32) >> 32);
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}
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extern IRExpr *getIReg(UInt);
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extern void putIReg(UInt, IRExpr *);
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/* Get value from accumulator (helper function for MIPS32 DSP ASE instructions).
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This function should be called before any other operation if widening
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multiplications are used. */
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extern IRExpr *getAcc(UInt acNo);
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extern IRExpr *getDSPControl(void);
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extern IRExpr *mkNarrowTo32(IRType, IRExpr *);
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extern void putLO(IRExpr *);
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extern void putHI(IRExpr *);
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/*------------------------------------------------------------*/
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/*--- Field helpers ---*/
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/*------------------------------------------------------------*/
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static inline UInt get_opcode(UInt mipsins)
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{
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return (0xFC000000 & mipsins) >> 26;
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}
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static inline UInt get_rs(UInt mipsins)
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{
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return (0x03E00000 & mipsins) >> 21;
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}
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static inline UInt get_rt(UInt mipsins)
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{
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return (0x001F0000 & mipsins) >> 16;
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}
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static inline UInt get_imm(UInt mipsins)
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{
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return (0x0000FFFF & mipsins);
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}
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static inline UInt get_instr_index(UInt mipsins)
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{
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return (0x03FFFFFF & mipsins);
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}
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static inline UInt get_rd(UInt mipsins)
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{
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return (0x0000F800 & mipsins) >> 11;
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}
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static inline UInt get_sa(UInt mipsins)
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{
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return (0x000007C0 & mipsins) >> 6;
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}
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static inline UInt get_function(UInt mipsins)
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{
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return (0x0000003F & mipsins);
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}
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static inline UInt get_ft(UInt mipsins)
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{
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return (0x001F0000 & mipsins) >> 16;
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}
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static inline UInt get_fs(UInt mipsins)
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{
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return (0x0000F800 & mipsins) >> 11;
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}
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static inline UInt get_fd(UInt mipsins)
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{
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return (0x000007C0 & mipsins) >> 6;
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}
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static inline UInt get_mov_cc(UInt mipsins)
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{
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return (0x001C0000 & mipsins) >> 18;
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}
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static inline UInt get_bc1_cc(UInt mipsins)
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{
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return (0x001C0000 & mipsins) >> 18;
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}
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static inline UInt get_fpc_cc(UInt mipsins)
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{
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return (0x00000700 & mipsins) >> 8;
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}
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static inline UInt get_tf(UInt mipsins)
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{
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return (0x00010000 & mipsins) >> 16;
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}
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static inline UInt get_nd(UInt mipsins)
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{
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return (0x00020000 & mipsins) >> 17;
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}
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static inline UInt get_fmt(UInt mipsins)
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{
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return (0x03E00000 & mipsins) >> 21;
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}
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static inline UInt get_FC(UInt mipsins)
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{
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return (0x000000F0 & mipsins) >> 4;
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}
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static inline UInt get_cond(UInt mipsins)
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{
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return (0x0000000F & mipsins);
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}
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/* for break & syscall */
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static inline UInt get_code(UInt mipsins)
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{
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return (0xFFC0 & mipsins) >> 6;
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}
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static inline UInt get_lsb(UInt mipsins)
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{
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return (0x7C0 & mipsins) >> 6;
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}
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static inline UInt get_msb(UInt mipsins)
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{
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return (0x0000F800 & mipsins) >> 11;
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}
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static inline UInt get_rot(UInt mipsins)
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{
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return (0x00200000 & mipsins) >> 21;
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}
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static inline UInt get_rotv(UInt mipsins)
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{
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return (0x00000040 & mipsins) >> 6;
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}
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static inline UInt get_sel(UInt mipsins)
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{
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return (0x00000007 & mipsins);
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}
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/* Get acc number for all MIPS32 DSP ASE(r2) instructions that use them,
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except for MFHI and MFLO. */
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static inline UInt get_acNo(UInt mipsins)
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{
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return (0x00001800 & mipsins) >> 11;
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}
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/* Get accumulator number for MIPS32 DSP ASEr2 MFHI and MFLO instructions. */
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static inline UInt get_acNo_mfhilo(UInt mipsins)
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{
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return (0x00600000 & mipsins) >> 21;
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}
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/* Get mask field (helper function for wrdsp instruction). */
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static inline UInt get_wrdspMask(UInt mipsins)
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{
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return (0x001ff800 & mipsins) >> 11;
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}
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/* Get mask field (helper function for rddsp instruction). */
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static inline UInt get_rddspMask(UInt mipsins)
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{
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return (0x03ff0000 & mipsins) >> 16;
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}
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/* Get shift field (helper function for DSP ASE instructions). */
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static inline UInt get_shift(UInt mipsins)
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{
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return (0x03f00000 & mipsins) >> 20;
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}
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/* Get immediate field for DSP ASE instructions. */
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static inline UInt get_dspImm(UInt mipsins)
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{
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return (0x03ff0000 & mipsins) >> 16;
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}
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#endif
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/*---------------------------------------------------------------*/
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/*--- end mips_defs.h ---*/
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/*---------------------------------------------------------------*/
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