mirror of
https://github.com/Zenithsiz/ftmemsim-valgrind.git
synced 2026-02-04 02:18:37 +00:00
Removed now-defunct read/write checks for FPU ops.
git-svn-id: svn://svn.valgrind.org/valgrind/trunk@3074
This commit is contained in:
Nicholas Nethercote
parent
196e8dfd25
commit
86751c1c2e
@ -69,9 +69,6 @@ extern REGPARM(1) UInt MC_(helperc_LOADV2) ( Addr );
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extern REGPARM(1) UInt MC_(helperc_LOADV4) ( Addr );
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extern REGPARM(1) ULong MC_(helperc_LOADV8) ( Addr );
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extern REGPARM(2) void MC_(fpu_write_check) ( Addr addr, SizeT size );
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extern REGPARM(2) void MC_(fpu_read_check) ( Addr addr, SizeT size );
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/* Functions defined in mc_errcontext.c */
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extern void MC_(record_value_error) ( ThreadId tid, Int size );
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extern void MC_(record_user_error) ( ThreadId tid, Addr a, Bool isWrite,
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@ -103,9 +103,6 @@ static void mc_wr_V4_SLOWLY ( Addr a, UInt vbytes );
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static void mc_wr_V2_SLOWLY ( Addr a, UInt vbytes );
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static void mc_wr_V1_SLOWLY ( Addr a, UInt vbytes );
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static void mc_fpu_read_check_SLOWLY ( Addr addr, SizeT size );
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static void mc_fpu_write_check_SLOWLY ( Addr addr, SizeT size );
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/*------------------------------------------------------------*/
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/*--- Data defns. ---*/
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/*------------------------------------------------------------*/
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@ -1362,243 +1359,6 @@ REGPARM(1) void MC_(helperc_complain_undef) ( HWord sz )
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}
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/* ---------------------------------------------------------------------
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FPU load and store checks, called from generated code.
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------------------------------------------------------------------ */
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REGPARM(2)
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void MC_(fpu_read_check) ( Addr addr, SizeT size )
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{
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/* Ensure the read area is both addressible and valid (ie,
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readable). If there's an address error, don't report a value
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error too; but if there isn't an address error, check for a
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value error.
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Try to be reasonably fast on the common case; wimp out and defer
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to mc_fpu_read_check_SLOWLY for everything else. */
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SecMap* sm;
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UInt sm_off, v_off, a_off;
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Addr addr4;
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PROF_EVENT(80);
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# ifdef VG_DEBUG_MEMORY
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mc_fpu_read_check_SLOWLY ( addr, size );
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# else
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if (size == 4) {
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if (!IS_ALIGNED4_ADDR(addr)) goto slow4;
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PROF_EVENT(81);
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/* Properly aligned. */
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sm = primary_map[addr >> 16];
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sm_off = addr & 0xFFFF;
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a_off = sm_off >> 3;
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if (sm->abits[a_off] != VGM_BYTE_VALID) goto slow4;
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/* Properly aligned and addressible. */
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v_off = addr & 0xFFFF;
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if (((UInt*)(sm->vbyte))[ v_off >> 2 ] != VGM_WORD_VALID)
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goto slow4;
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/* Properly aligned, addressible and with valid data. */
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return;
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slow4:
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mc_fpu_read_check_SLOWLY ( addr, 4 );
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return;
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}
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if (size == 8) {
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if (!IS_ALIGNED4_ADDR(addr)) goto slow8;
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PROF_EVENT(82);
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/* Properly aligned. Do it in two halves. */
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addr4 = addr + 4;
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/* First half. */
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sm = primary_map[addr >> 16];
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sm_off = addr & 0xFFFF;
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a_off = sm_off >> 3;
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if (sm->abits[a_off] != VGM_BYTE_VALID) goto slow8;
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/* First half properly aligned and addressible. */
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v_off = addr & 0xFFFF;
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if (((UInt*)(sm->vbyte))[ v_off >> 2 ] != VGM_WORD_VALID)
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goto slow8;
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/* Second half. */
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sm = primary_map[addr4 >> 16];
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sm_off = addr4 & 0xFFFF;
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a_off = sm_off >> 3;
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if (sm->abits[a_off] != VGM_BYTE_VALID) goto slow8;
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/* Second half properly aligned and addressible. */
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v_off = addr4 & 0xFFFF;
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if (((UInt*)(sm->vbyte))[ v_off >> 2 ] != VGM_WORD_VALID)
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goto slow8;
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/* Both halves properly aligned, addressible and with valid
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data. */
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return;
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slow8:
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mc_fpu_read_check_SLOWLY ( addr, 8 );
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return;
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}
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/* Can't be bothered to huff'n'puff to make these (allegedly) rare
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cases go quickly. */
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if (size == 2) {
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PROF_EVENT(83);
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mc_fpu_read_check_SLOWLY ( addr, 2 );
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return;
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}
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if (size == 16 /*SSE*/
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|| size == 10 || size == 28 || size == 108 || size == 512) {
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PROF_EVENT(84);
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mc_fpu_read_check_SLOWLY ( addr, size );
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return;
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}
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VG_(printf)("size is %d\n", size);
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VG_(tool_panic)("MC_(fpu_read_check): unhandled size");
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# endif
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}
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REGPARM(2)
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void MC_(fpu_write_check) ( Addr addr, SizeT size )
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{
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/* Ensure the written area is addressible, and moan if otherwise.
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If it is addressible, make it valid, otherwise invalid.
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*/
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SecMap* sm;
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UInt sm_off, v_off, a_off;
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Addr addr4;
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PROF_EVENT(85);
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# ifdef VG_DEBUG_MEMORY
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mc_fpu_write_check_SLOWLY ( addr, size );
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# else
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if (size == 4) {
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if (!IS_ALIGNED4_ADDR(addr)) goto slow4;
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PROF_EVENT(86);
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/* Properly aligned. */
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sm = primary_map[addr >> 16];
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sm_off = addr & 0xFFFF;
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a_off = sm_off >> 3;
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if (sm->abits[a_off] != VGM_BYTE_VALID) goto slow4;
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/* Properly aligned and addressible. Make valid. */
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v_off = addr & 0xFFFF;
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((UInt*)(sm->vbyte))[ v_off >> 2 ] = VGM_WORD_VALID;
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return;
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slow4:
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mc_fpu_write_check_SLOWLY ( addr, 4 );
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return;
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}
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if (size == 8) {
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if (!IS_ALIGNED4_ADDR(addr)) goto slow8;
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PROF_EVENT(87);
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/* Properly aligned. Do it in two halves. */
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addr4 = addr + 4;
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/* First half. */
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sm = primary_map[addr >> 16];
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sm_off = addr & 0xFFFF;
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a_off = sm_off >> 3;
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if (sm->abits[a_off] != VGM_BYTE_VALID) goto slow8;
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/* First half properly aligned and addressible. Make valid. */
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v_off = addr & 0xFFFF;
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((UInt*)(sm->vbyte))[ v_off >> 2 ] = VGM_WORD_VALID;
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/* Second half. */
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sm = primary_map[addr4 >> 16];
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sm_off = addr4 & 0xFFFF;
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a_off = sm_off >> 3;
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if (sm->abits[a_off] != VGM_BYTE_VALID) goto slow8;
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/* Second half properly aligned and addressible. */
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v_off = addr4 & 0xFFFF;
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((UInt*)(sm->vbyte))[ v_off >> 2 ] = VGM_WORD_VALID;
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/* Properly aligned, addressible and with valid data. */
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return;
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slow8:
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mc_fpu_write_check_SLOWLY ( addr, 8 );
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return;
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}
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/* Can't be bothered to huff'n'puff to make these (allegedly) rare
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cases go quickly. */
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if (size == 2) {
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PROF_EVENT(88);
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mc_fpu_write_check_SLOWLY ( addr, 2 );
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return;
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}
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if (size == 16 /*SSE*/
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|| size == 10 || size == 28 || size == 108 || size == 512) {
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PROF_EVENT(89);
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mc_fpu_write_check_SLOWLY ( addr, size );
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return;
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}
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VG_(printf)("size is %d\n", size);
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VG_(tool_panic)("MC_(fpu_write_check): unhandled size");
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# endif
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}
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/* ---------------------------------------------------------------------
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Slow, general cases for FPU load and store checks.
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------------------------------------------------------------------ */
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/* Generic version. Test for both addr and value errors, but if
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there's an addr error, don't report a value error even if it
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exists. */
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void mc_fpu_read_check_SLOWLY ( Addr addr, SizeT size )
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{
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Int i;
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Bool aerr = False;
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Bool verr = False;
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PROF_EVENT(90);
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for (i = 0; i < size; i++) {
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PROF_EVENT(91);
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if (get_abit(addr+i) != VGM_BIT_VALID)
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aerr = True;
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if (get_vbyte(addr+i) != VGM_BYTE_VALID)
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verr = True;
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}
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if (aerr) {
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MAC_(record_address_error)( VG_(get_current_tid)(), addr, size, False );
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} else {
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if (verr)
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MC_(record_value_error)( VG_(get_current_tid)(), size );
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}
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}
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/* Generic version. Test for addr errors. Valid addresses are
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given valid values, and invalid addresses invalid values. */
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void mc_fpu_write_check_SLOWLY ( Addr addr, SizeT size )
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{
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Int i;
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Addr a_here;
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Bool a_ok;
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Bool aerr = False;
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PROF_EVENT(92);
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for (i = 0; i < size; i++) {
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PROF_EVENT(93);
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a_here = addr+i;
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a_ok = get_abit(a_here) == VGM_BIT_VALID;
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if (a_ok) {
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set_vbyte(a_here, VGM_BYTE_VALID);
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} else {
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set_vbyte(a_here, VGM_BYTE_INVALID);
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aerr = True;
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}
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}
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if (aerr) {
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MAC_(record_address_error)( VG_(get_current_tid)(), addr, size, True );
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}
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}
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/*------------------------------------------------------------*/
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/*--- Metadata get/set functions, for client requests. ---*/
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/*------------------------------------------------------------*/
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