mirror of
https://github.com/Zenithsiz/ftmemsim-valgrind.git
synced 2026-02-04 02:18:37 +00:00
DRD: Make --trace-addr work for atomic loads and stores. To do: update manual
git-svn-id: svn://svn.valgrind.org/valgrind/trunk@12291
This commit is contained in:
Bart Van Assche
parent
ffcd373429
commit
606de3587f
@ -307,26 +307,82 @@ static Bool is_stack_access(IRSB* const bb, IRExpr* const addr_expr)
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return result;
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}
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static void instrument_load(IRSB* const bb,
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IRExpr* const addr_expr,
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const HWord size)
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static const IROp u_widen_irop[5][9] = {
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[1][2] = Iop_8Uto16,
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[1][4] = Iop_8Uto32,
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[1][8] = Iop_8Uto64,
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[2][4] = Iop_16Uto32,
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[2][8] = Iop_16Uto64,
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[4][8] = Iop_32Uto64,
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};
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static void trace_mem_store(IRSB* const bb, IRExpr* const addr_expr,
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IRExpr* const data_expr)
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{
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IRExpr *hword_data_expr;
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HWord size;
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size = sizeofIRType(typeOfIRExpr(bb->tyenv, data_expr));
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if (size == sizeof(HWord)) {
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hword_data_expr = data_expr;
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} else {
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IROp widen_op;
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tl_assert(sizeof(HWord) == 4 || sizeof(HWord) == 8);
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if (size < sizeof(u_widen_irop)/sizeof(u_widen_irop[0])) {
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widen_op = u_widen_irop[size][sizeof(HWord)];
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if (!widen_op)
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widen_op = Iop_INVALID;
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} else {
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widen_op = Iop_INVALID;
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}
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if (widen_op != Iop_INVALID) {
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IRTemp tmp;
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tmp = newIRTemp(bb->tyenv, sizeof(HWord) == 4 ? Ity_I32 : Ity_I64);
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addStmtToIRSB(bb,
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IRStmt_WrTmp(tmp, IRExpr_Unop(widen_op, data_expr)));
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hword_data_expr = IRExpr_RdTmp(tmp);
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} else {
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hword_data_expr = mkIRExpr_HWord(0);
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}
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}
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addStmtToIRSB(bb,
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IRStmt_Dirty(
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unsafeIRDirty_0_N(/*regparms*/3,
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"drd_trace_mem_store",
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VG_(fnptr_to_fnentry)
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(drd_trace_mem_store),
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mkIRExprVec_3(addr_expr, mkIRExpr_HWord(size),
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hword_data_expr))));
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}
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static void instrument_load(IRSB* const bb, IRExpr* const addr_expr,
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const HWord size, IRExpr* const data_expr,
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Bool is_store)
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{
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IRExpr* size_expr;
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IRExpr** argv;
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IRDirty* di;
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if (UNLIKELY(DRD_(any_address_is_traced)()))
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{
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addStmtToIRSB(bb,
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IRStmt_Dirty(
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unsafeIRDirty_0_N(/*regparms*/2,
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"drd_trace_mem_load",
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VG_(fnptr_to_fnentry)
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(drd_trace_mem_load),
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mkIRExprVec_2(addr_expr, mkIRExpr_HWord(size)))));
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if (UNLIKELY(DRD_(any_address_is_traced)())) {
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if (is_store) {
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tl_assert(data_expr);
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trace_mem_store(bb, addr_expr, data_expr);
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} else {
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addStmtToIRSB(bb,
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IRStmt_Dirty(
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unsafeIRDirty_0_N(/*regparms*/2,
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"drd_trace_mem_load",
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VG_(fnptr_to_fnentry)
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(drd_trace_mem_load),
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mkIRExprVec_2(addr_expr,
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mkIRExpr_HWord(size)))));
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}
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}
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if (! s_check_stack_accesses && is_stack_access(bb, addr_expr))
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if (!s_check_stack_accesses && is_stack_access(bb, addr_expr))
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return;
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switch (size)
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@ -371,15 +427,6 @@ static void instrument_load(IRSB* const bb,
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addStmtToIRSB(bb, IRStmt_Dirty(di));
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}
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static const IROp u_widen_irop[5][9] = {
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[1][2] = Iop_8Uto16,
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[1][4] = Iop_8Uto32,
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[1][8] = Iop_8Uto64,
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[2][4] = Iop_16Uto32,
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[2][8] = Iop_16Uto64,
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[4][8] = Iop_32Uto64,
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};
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static void instrument_store(IRSB* const bb, IRExpr* const addr_expr,
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IRExpr* const data_expr)
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{
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@ -391,42 +438,7 @@ static void instrument_store(IRSB* const bb, IRExpr* const addr_expr,
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size = sizeofIRType(typeOfIRExpr(bb->tyenv, data_expr));
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if (UNLIKELY(DRD_(any_address_is_traced)()))
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{
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IRExpr *hword_data_expr;
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if (size == sizeof(HWord)) {
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hword_data_expr = data_expr;
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} else {
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IROp widen_op;
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tl_assert(sizeof(HWord) == 4 || sizeof(HWord) == 8);
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if (size < sizeof(u_widen_irop)/sizeof(u_widen_irop[0])) {
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widen_op = u_widen_irop[size][sizeof(HWord)];
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if (!widen_op)
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widen_op = Iop_INVALID;
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} else {
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widen_op = Iop_INVALID;
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}
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if (widen_op != Iop_INVALID) {
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IRTemp tmp;
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tmp = newIRTemp(bb->tyenv, sizeof(HWord) == 4 ? Ity_I32 : Ity_I64);
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addStmtToIRSB(bb,
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IRStmt_WrTmp(tmp, IRExpr_Unop(widen_op, data_expr)));
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hword_data_expr = IRExpr_RdTmp(tmp);
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} else {
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hword_data_expr = mkIRExpr_HWord(0);
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}
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}
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addStmtToIRSB(bb,
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IRStmt_Dirty(
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unsafeIRDirty_0_N(/*regparms*/3,
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"drd_trace_mem_store",
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VG_(fnptr_to_fnentry)
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(drd_trace_mem_store),
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mkIRExprVec_3(addr_expr, mkIRExpr_HWord(size),
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hword_data_expr))));
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}
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trace_mem_store(bb, addr_expr, data_expr);
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if (!s_check_stack_accesses && is_stack_access(bb, addr_expr))
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return;
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@ -530,15 +542,11 @@ IRSB* DRD_(instrument)(VgCallbackClosure* const closure,
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break;
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case Ist_WrTmp:
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if (instrument)
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{
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if (instrument) {
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const IRExpr* const data = st->Ist.WrTmp.data;
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if (data->tag == Iex_Load)
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{
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instrument_load(bb,
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data->Iex.Load.addr,
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sizeofIRType(data->Iex.Load.ty));
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}
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instrument_load(bb, data->Iex.Load.addr,
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sizeofIRType(data->Iex.Load.ty), NULL, False);
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}
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addStmtToIRSB(bb, st);
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break;
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@ -600,29 +608,26 @@ IRSB* DRD_(instrument)(VgCallbackClosure* const closure,
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dataSize = sizeofIRType(typeOfIRExpr(bb->tyenv, cas->dataLo));
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if (cas->dataHi != NULL)
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dataSize *= 2; /* since it's a doubleword-CAS */
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instrument_load(bb, cas->addr, dataSize);
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instrument_load(bb, cas->addr, dataSize, cas->dataLo, True);
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}
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addStmtToIRSB(bb, st);
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break;
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case Ist_LLSC: {
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/* Ignore store-conditionals, and handle load-linked's
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exactly like normal loads. */
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/*
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* Ignore store-conditionals (except for tracing), and handle
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* load-linked's exactly like normal loads.
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*/
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IRType dataTy;
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if (st->Ist.LLSC.storedata == NULL)
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{
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if (st->Ist.LLSC.storedata == NULL) {
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/* LL */
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dataTy = typeOfIRTemp(bb_in->tyenv, st->Ist.LLSC.result);
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if (instrument) {
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instrument_load(bb,
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st->Ist.LLSC.addr,
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sizeofIRType(dataTy));
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}
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}
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else
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{
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if (instrument)
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instrument_load(bb, st->Ist.LLSC.addr, sizeofIRType(dataTy),
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NULL, False);
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} else {
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/* SC */
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/*ignore */
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trace_mem_store(bb, st->Ist.LLSC.addr, st->Ist.LLSC.storedata);
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}
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addStmtToIRSB(bb, st);
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break;
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