mirror of
https://github.com/Zenithsiz/ftmemsim-valgrind.git
synced 2026-02-05 11:10:21 +00:00
Added Helgrind regression tests tc05, tc06 and tc08.
git-svn-id: svn://svn.valgrind.org/valgrind/trunk@7476
This commit is contained in:
parent
6475f5e25b
commit
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@ -19,24 +19,25 @@ EXTRA_DIST = $(noinst_SCRIPTS) \
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fp_race.stderr.exp2 \
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fp_race2.vgtest \
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fp_race2.stdout.exp fp_race2.stderr.exp \
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hg01_all_ok.vgtest \
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hg01_all_ok.stderr.exp \
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hg02_deadlock.vgtest \
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hg02_deadlock.stderr.exp \
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hg03_inherit.vgtest \
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hg03_inherit.stderr.exp \
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hg01_all_ok.vgtest \
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hg01_all_ok.stderr.exp \
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hg02_deadlock.vgtest \
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hg02_deadlock.stderr.exp \
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hg03_inherit.vgtest \
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hg03_inherit.stderr.exp \
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hg03_inherit.stderr.exp2 \
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hg04_race.vgtest \
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hg04_race.stderr.exp \
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hg04_race.vgtest \
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hg04_race.stderr.exp \
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hg04_race.stderr.exp2 \
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hg05_race2.vgtest \
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hg05_race2.stderr.exp \
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hg06_readshared.vgtest \
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hg06_readshared.stderr.exp \
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hg05_race2.vgtest \
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hg05_race2.stderr.exp \
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hg06_readshared.vgtest \
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hg06_readshared.stderr.exp \
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matinv.vgtest \
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matinv.stdout.exp matinv.stderr.exp \
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pth_barrier.vgtest \
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pth_barrier.stderr.exp \
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pth_barrier.vgtest pth_barrier.stderr.exp \
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pth_barrier2.vgtest pth_barrier2.stderr.exp \
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pth_barrier3.vgtest pth_barrier3.stderr.exp \
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pth_broadcast.vgtest \
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pth_broadcast.stdout.exp pth_broadcast.stderr.exp \
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pth_cond_race.vgtest \
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@ -53,52 +54,58 @@ EXTRA_DIST = $(noinst_SCRIPTS) \
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sem_as_mutex.stderr.exp sem_as_mutex.stderr.exp2 \
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sem_as_mutex2.vgtest \
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sem_as_mutex2.stderr.exp \
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tc01_simple_race.vgtest \
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tc01_simple_race.stderr.exp \
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tc01_simple_race.vgtest \
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tc01_simple_race.stderr.exp \
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tc01_simple_race.stderr.exp2 \
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tc02_simple_tls.vgtest \
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tc02_simple_tls.stderr.exp \
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tc03_re_excl.vgtest \
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tc03_re_excl.stderr.exp \
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tc04_free_lock.vgtest \
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tc04_free_lock.stderr.exp \
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tc07_hbl1.vgtest \
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tc07_hbl1.stderr.exp tc07_hbl1.stdout.exp \
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tc02_simple_tls.vgtest \
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tc02_simple_tls.stderr.exp \
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tc03_re_excl.vgtest \
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tc03_re_excl.stderr.exp \
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tc04_free_lock.vgtest \
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tc04_free_lock.stderr.exp \
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tc05_simple_race.vgtest \
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tc05_simple_race.stderr.exp \
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tc06_two_races.vgtest \
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tc06_two_races.stderr.exp \
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tc07_hbl1.vgtest \
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tc07_hbl1.stderr.exp tc07_hbl1.stdout.exp \
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tc07_hbl1.stderr.exp2 \
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tc09_bad_unlock.vgtest \
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tc09_bad_unlock.stderr.exp \
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tc10_rec_lock.vgtest \
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tc10_rec_lock.stderr.exp \
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tc11_XCHG.vgtest \
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tc11_XCHG.stderr.exp tc11_XCHG.stdout.exp \
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tc08_hbl2.vgtest \
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tc08_hbl2.stderr.exp \
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tc09_bad_unlock.vgtest \
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tc09_bad_unlock.stderr.exp \
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tc10_rec_lock.vgtest \
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tc10_rec_lock.stderr.exp \
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tc11_XCHG.vgtest \
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tc11_XCHG.stderr.exp tc11_XCHG.stdout.exp \
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tc11_XCHG.stderr.exp2 \
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tc12_rwl_trivial.vgtest \
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tc12_rwl_trivial.stderr.exp \
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tc13_laog1.vgtest \
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tc13_laog1.stderr.exp \
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tc15_laog_lockdel.vgtest \
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tc15_laog_lockdel.stderr.exp \
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tc16_byterace.vgtest \
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tc16_byterace.stderr.exp \
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tc12_rwl_trivial.vgtest \
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tc12_rwl_trivial.stderr.exp \
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tc13_laog1.vgtest \
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tc13_laog1.stderr.exp \
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tc15_laog_lockdel.vgtest \
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tc15_laog_lockdel.stderr.exp \
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tc16_byterace.vgtest \
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tc16_byterace.stderr.exp \
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tc16_byterace.stderr.exp2 \
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tc17_sembar.vgtest \
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tc17_sembar.stderr.exp \
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tc18_semabuse.vgtest \
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tc18_semabuse.stderr.exp \
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tc19_shadowmem.vgtest \
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tc19_shadowmem.stderr.exp \
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tc20_verifywrap.vgtest \
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tc20_verifywrap.stderr.exp \
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tc17_sembar.vgtest \
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tc17_sembar.stderr.exp \
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tc18_semabuse.vgtest \
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tc18_semabuse.stderr.exp \
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tc19_shadowmem.vgtest \
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tc19_shadowmem.stderr.exp \
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tc20_verifywrap.vgtest \
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tc20_verifywrap.stderr.exp \
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tc20_verifywrap.stderr.exp2 \
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tc21_pthonce.vgtest \
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tc21_pthonce.stderr.exp tc21_pthonce.stdout.exp \
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tc22_exit_w_lock.vgtest \
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tc22_exit_w_lock.stderr.exp \
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tc21_pthonce.vgtest \
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tc21_pthonce.stderr.exp tc21_pthonce.stdout.exp \
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tc22_exit_w_lock.vgtest \
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tc22_exit_w_lock.stderr.exp \
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tc22_exit_w_lock.stderr.exp-32bit \
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tc23_bogus_condwait.vgtest \
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tc23_bogus_condwait.stderr.exp \
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tc24_nonzero_sem.vgtest \
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tc24_nonzero_sem.stderr.exp \
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tc23_bogus_condwait.vgtest \
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tc23_bogus_condwait.stderr.exp \
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tc24_nonzero_sem.vgtest \
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tc24_nonzero_sem.stderr.exp \
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sigalrm.vgtest \
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sigalrm.stdout.exp sigalrm.stderr.exp
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@ -126,7 +133,10 @@ check_PROGRAMS = \
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tc02_simple_tls \
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tc03_re_excl \
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tc04_free_lock \
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tc05_simple_race \
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tc06_two_races \
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tc07_hbl1 \
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tc08_hbl2 \
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tc09_bad_unlock \
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tc10_rec_lock \
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tc11_XCHG \
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@ -143,9 +153,6 @@ check_PROGRAMS = \
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tc23_bogus_condwait \
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tc24_nonzero_sem
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# tc05_simple_race -- result depends on scheduler.
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# tc06_two_races -- result depends on scheduler.
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# tc08_hbl2 -- result depends on scheduler.
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# tc14_laog_dinphils -- hangs.
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@ -206,9 +213,18 @@ tc03_re_excl_LDADD = -lpthread
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tc04_free_lock_SOURCES = ../../helgrind/tests/tc04_free_lock.c
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tc04_free_lock_LDADD = -lpthread
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tc05_simple_race_SOURCES = ../../helgrind/tests/tc05_simple_race.c
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tc05_simple_race_LDADD = -lpthread
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tc06_two_races_SOURCES = ../../helgrind/tests/tc06_two_races.c
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tc06_two_races_LDADD = -lpthread
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tc07_hbl1_SOURCES = ../../helgrind/tests/tc07_hbl1.c
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tc07_hbl1_LDADD = -lpthread
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tc08_hbl2_SOURCES = ../../helgrind/tests/tc08_hbl2.c
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tc08_hbl2_LDADD = -lpthread
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tc09_bad_unlock_SOURCES = ../../helgrind/tests/tc09_bad_unlock.c
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tc09_bad_unlock_LDADD = -lpthread
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1
exp-drd/tests/tc05_simple_race.stderr.exp
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1
exp-drd/tests/tc05_simple_race.stderr.exp
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@ -0,0 +1 @@
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ERROR SUMMARY: 2 errors from 2 contexts
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2
exp-drd/tests/tc05_simple_race.vgtest
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2
exp-drd/tests/tc05_simple_race.vgtest
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@ -0,0 +1,2 @@
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prog: tc05_simple_race
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stderr_filter: filter_error_summary
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1
exp-drd/tests/tc06_two_races.stderr.exp
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1
exp-drd/tests/tc06_two_races.stderr.exp
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@ -0,0 +1 @@
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ERROR SUMMARY: 2 errors from 2 contexts
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2
exp-drd/tests/tc06_two_races.vgtest
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2
exp-drd/tests/tc06_two_races.vgtest
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@ -0,0 +1,2 @@
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prog: tc06_two_races
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stderr_filter: filter_error_summary
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1
exp-drd/tests/tc08_hbl2.stderr.exp
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1
exp-drd/tests/tc08_hbl2.stderr.exp
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@ -0,0 +1 @@
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ERROR SUMMARY: 16 errors from 16 contexts
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3
exp-drd/tests/tc08_hbl2.stdout.exp
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3
exp-drd/tests/tc08_hbl2.stdout.exp
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@ -0,0 +1,3 @@
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child: new value 6
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child: new value 10
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done, x = 10
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2
exp-drd/tests/tc08_hbl2.vgtest
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2
exp-drd/tests/tc08_hbl2.vgtest
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@ -0,0 +1,2 @@
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prog: tc08_hbl2
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stderr_filter: filter_error_summary
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