mirror of
https://github.com/Zenithsiz/ftmemsim-valgrind.git
synced 2026-02-04 02:18:37 +00:00
Add test cases for 32-bit v8 FP and SIMD insns.
git-svn-id: svn://svn.valgrind.org/valgrind/trunk@16194
This commit is contained in:
Julian Seward
parent
f898cb0e21
commit
2a218b7efc
485
none/tests/arm/v8fpsimd_a.c
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485
none/tests/arm/v8fpsimd_a.c
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@ -0,0 +1,485 @@
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/*
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gcc -o v8fpsimd_a v8fpsimd_a.c -march=armv8-a -mfpu=crypto-neon-fp-armv8 \
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-I../../.. -Wall -g -marm
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*/
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#include <stdio.h>
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#include <assert.h>
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#include <malloc.h> // memalign
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#include <string.h> // memset
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#include "tests/malloc.h"
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#include <math.h> // isnormal
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typedef unsigned char UChar;
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typedef unsigned short int UShort;
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typedef unsigned int UInt;
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typedef signed int Int;
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typedef unsigned char UChar;
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typedef unsigned long long int ULong;
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typedef signed long long int Long;
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typedef double Double;
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typedef float Float;
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typedef unsigned char Bool;
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#define False ((Bool)0)
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#define True ((Bool)1)
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#define ITERS 1
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typedef
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enum { TyHF=1234, TySF, TyDF, TyB, TyH, TyS, TyD, TyNONE }
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LaneTy;
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union _V128 {
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UChar u8[16];
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UShort u16[8];
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UInt u32[4];
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ULong u64[2];
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Float f32[4];
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Double f64[2];
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};
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typedef union _V128 V128;
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static inline UChar randUChar ( void )
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{
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static UInt seed = 80021;
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seed = 1103515245 * seed + 12345;
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return (seed >> 17) & 0xFF;
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}
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//static ULong randULong ( LaneTy ty )
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//{
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// Int i;
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// ULong r = 0;
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// for (i = 0; i < 8; i++) {
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// r = (r << 8) | (ULong)(0xFF & randUChar());
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// }
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// return r;
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//}
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/* Generates a random V128. Ensures that that it contains normalised
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FP numbers when viewed as either F32x4 or F64x2, so that it is
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reasonable to use in FP test cases. */
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static void randV128 ( /*OUT*/V128* v, LaneTy ty )
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{
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static UInt nCalls = 0, nIters = 0;
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Int i;
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nCalls++;
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while (1) {
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nIters++;
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for (i = 0; i < 16; i++) {
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v->u8[i] = randUChar();
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}
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if (randUChar() < 32) {
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/* once every 8 times, clone one of the lanes */
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switch (ty) {
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case TySF: case TyS: {
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UInt l1, l2;
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while (1) {
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l1 = randUChar() & 3;
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l2 = randUChar() & 3;
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if (l1 != l2) break;
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}
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assert(l1 < 4 && l2 < 4);
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v->u32[l1] = v->u32[l2];
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printf("randV128: doing v->u32[%u] = v->u32[%u]\n", l1, l2);
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break;
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}
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case TyDF: case TyD: {
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UInt l1, l2;
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while (1) {
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l1 = randUChar() & 1;
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l2 = randUChar() & 1;
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if (l1 != l2) break;
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}
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assert(l1 < 2 && l2 < 2);
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printf("randV128: doing v->u64[%u] = v->u64[%u]\n", l1, l2);
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v->u64[l1] = v->u64[l2];
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break;
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}
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default:
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break;
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}
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}
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if (isnormal(v->f32[0]) && isnormal(v->f32[1]) && isnormal(v->f32[2])
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&& isnormal(v->f32[3]) && isnormal(v->f64[0]) && isnormal(v->f64[1]))
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break;
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}
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if (0 == (nCalls & 0xFF))
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printf("randV128: %u calls, %u iters\n", nCalls, nIters);
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}
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static void showV128 ( V128* v )
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{
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Int i;
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for (i = 15; i >= 0; i--)
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printf("%02x", (Int)v->u8[i]);
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}
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//static void showBlock ( const char* msg, V128* block, Int nBlock )
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//{
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// Int i;
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// printf("%s\n", msg);
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// for (i = 0; i < nBlock; i++) {
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// printf(" ");
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// showV128(&block[i]);
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// printf("\n");
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// }
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//}
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/* ---------------------------------------------------------------- */
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/* -- Parameterisable test macros -- */
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/* ---------------------------------------------------------------- */
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#define DO50(_action) \
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do { \
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Int _qq; for (_qq = 0; _qq < 50; _qq++) { _action ; } \
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} while (0)
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/* Generate a test that involves two vector regs,
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with no bias as towards which is input or output.
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It's OK to use r8 as scratch.
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Note that the insn doesn't *have* to use Q (128 bit) registers --
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it can instead mention D (64 bit) and S (32-bit) registers.
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However, in that case callers of this macro must be very careful to
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specify QVECREG1NO and QVECREG2NO in such a way as to cover all of
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the mentioned D and S registers, using the relations
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D<n> == S<2n+1> and S<2n>
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Q<n> == D<2n+1> and D<2n>
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Failing to do so correctly will make the test meaningless, because
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it will potentially load test data into the wrong registers before
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the test, and/or show the values of the wrong registers after the
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test. The allowed register values are:
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S: 0 .. 31
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D: 0 .. 31
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Q: 0 .. 15
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Note that Q[15..0] == D[31..0] but S[31..0] only overlaps Q[0..7],
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so a Q value of 8 or above is definitely invalid for a S register.
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None of this is checked, though, so be careful when creating the
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Q numbers.
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*/
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#define GEN_TWOVEC_QDS_TEST(TESTNAME,INSN,QVECREG1NO,QVECREG2NO) \
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__attribute__((noinline)) \
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static void test_##TESTNAME ( LaneTy ty ) { \
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Int i; \
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assert(QVECREG1NO >= 0 && QVECREG1NO <= 15); \
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assert(QVECREG2NO >= 0 && QVECREG2NO <= 15); \
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for (i = 0; i < ITERS; i++) { \
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V128 block[4+1]; \
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memset(block, 0x55, sizeof(block)); \
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randV128(&block[0], ty); \
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randV128(&block[1], ty); \
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randV128(&block[2], ty); \
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randV128(&block[3], ty); \
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__asm__ __volatile__( \
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"mov r9, #0 ; vmsr fpscr, r9 ; " \
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"add r9, %0, #0 ; vld1.8 { q"#QVECREG1NO" }, [r9] ; " \
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"add r9, %0, #16 ; vld1.8 { q"#QVECREG2NO" }, [r9] ; " \
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INSN " ; " \
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"add r9, %0, #32 ; vst1.8 { q"#QVECREG1NO" }, [r9] ; " \
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"add r9, %0, #48 ; vst1.8 { q"#QVECREG2NO" }, [r9] ; " \
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"vmrs r9, fpscr ; str r9, [%0, #64] " \
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: : "r"(&block[0]) \
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: "cc", "memory", "q"#QVECREG1NO, "q"#QVECREG2NO, "r8", "r9" \
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); \
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printf(INSN " "); \
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UInt fpscr = 0xFFFFFFFF & block[4].u32[0]; \
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showV128(&block[0]); printf(" "); \
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showV128(&block[1]); printf(" "); \
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showV128(&block[2]); printf(" "); \
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showV128(&block[3]); printf(" fpscr=%08x\n", fpscr); \
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} \
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}
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/* Generate a test that involves three vector regs,
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with no bias as towards which is input or output. It's also OK
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to use r8 as scratch. */
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#define GEN_THREEVEC_QDS_TEST(TESTNAME,INSN,QVECREG1NO,QVECREG2NO,QVECREG3NO) \
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__attribute__((noinline)) \
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static void test_##TESTNAME ( LaneTy ty ) { \
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Int i; \
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assert(QVECREG1NO >= 0 && QVECREG1NO <= 15); \
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assert(QVECREG2NO >= 0 && QVECREG2NO <= 15); \
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assert(QVECREG3NO >= 0 && QVECREG3NO <= 15); \
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for (i = 0; i < ITERS; i++) { \
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V128 block[6+1]; \
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memset(block, 0x55, sizeof(block)); \
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randV128(&block[0], ty); \
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randV128(&block[1], ty); \
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randV128(&block[2], ty); \
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randV128(&block[3], ty); \
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randV128(&block[4], ty); \
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randV128(&block[5], ty); \
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__asm__ __volatile__( \
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"mov r9, #0 ; vmsr fpscr, r9 ; " \
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"add r9, %0, #0 ; vld1.8 { q"#QVECREG1NO" }, [r9] ; " \
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"add r9, %0, #16 ; vld1.8 { q"#QVECREG2NO" }, [r9] ; " \
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"add r9, %0, #32 ; vld1.8 { q"#QVECREG3NO" }, [r9] ; " \
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INSN " ; " \
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"add r9, %0, #48 ; vst1.8 { q"#QVECREG1NO" }, [r9] ; " \
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"add r9, %0, #64 ; vst1.8 { q"#QVECREG2NO" }, [r9] ; " \
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"add r9, %0, #80 ; vst1.8 { q"#QVECREG3NO" }, [r9] ; " \
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"vmrs r9, fpscr ; str r9, [%0, #96] " \
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: : "r"(&block[0]) \
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: "cc", "memory", "q"#QVECREG1NO, "q"#QVECREG2NO, "q"#QVECREG3NO, \
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"r8", "r9" \
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); \
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printf(INSN " "); \
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UInt fpscr = 0xFFFFFFFF & block[6].u32[0]; \
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showV128(&block[0]); printf(" "); \
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showV128(&block[1]); printf(" "); \
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showV128(&block[2]); printf(" "); \
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showV128(&block[3]); printf(" "); \
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showV128(&block[4]); printf(" "); \
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showV128(&block[5]); printf(" fpscr=%08x\n", fpscr); \
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} \
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}
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GEN_THREEVEC_QDS_TEST(vselge_f32, "vselge.f32 s15,s16,s20", 3,4,5)
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GEN_THREEVEC_QDS_TEST(vselge_f64, "vselge.f64 d7, d8, d10", 3,4,5)
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GEN_THREEVEC_QDS_TEST(vselgt_f32, "vselgt.f32 s15,s16,s20", 3,4,5)
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GEN_THREEVEC_QDS_TEST(vselgt_f64, "vselgt.f64 d7, d8, d10", 3,4,5)
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GEN_THREEVEC_QDS_TEST(vseleq_f32, "vseleq.f32 s15,s16,s20", 3,4,5)
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GEN_THREEVEC_QDS_TEST(vseleq_f64, "vseleq.f64 d7, d8, d10", 3,4,5)
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GEN_THREEVEC_QDS_TEST(vselvs_f32, "vselvs.f32 s15,s16,s20", 3,4,5)
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GEN_THREEVEC_QDS_TEST(vselvs_f64, "vselvs.f64 d7, d8, d10", 3,4,5)
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GEN_THREEVEC_QDS_TEST(vmaxnm_f32, "vmaxnm.f32 s15,s16,s20", 3,4,5)
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GEN_THREEVEC_QDS_TEST(vmaxnm_f64, "vmaxnm.f64 d7, d8, d10", 3,4,5)
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GEN_THREEVEC_QDS_TEST(vminnm_f32, "vminnm.f32 s15,s16,s20", 3,4,5)
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GEN_THREEVEC_QDS_TEST(vminnm_f64, "vminnm.f64 d7, d8, d10", 3,4,5)
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GEN_TWOVEC_QDS_TEST(vcvtn_s32_f64, "vcvtn.s32.f64 s27, d5", 6,2)
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GEN_TWOVEC_QDS_TEST(vcvta_s32_f64, "vcvta.s32.f64 s4, d20", 1,10)
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GEN_TWOVEC_QDS_TEST(vcvtp_s32_f64, "vcvtp.s32.f64 s7, d31", 1,15)
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GEN_TWOVEC_QDS_TEST(vcvtm_s32_f64, "vcvtm.s32.f64 s1, d0", 0,0)
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GEN_TWOVEC_QDS_TEST(vcvtn_s32_f32, "vcvtn.s32.f32 s27, s5", 6,1)
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GEN_TWOVEC_QDS_TEST(vcvta_s32_f32, "vcvta.s32.f32 s4, s20", 1,5)
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GEN_TWOVEC_QDS_TEST(vcvtp_s32_f32, "vcvtp.s32.f32 s7, s31", 1,7)
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GEN_TWOVEC_QDS_TEST(vcvtm_s32_f32, "vcvtm.s32.f32 s1, s0", 0,0)
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GEN_TWOVEC_QDS_TEST(vcvtn_u32_f64, "vcvtn.u32.f64 s27, d5", 6,2)
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GEN_TWOVEC_QDS_TEST(vcvta_u32_f64, "vcvta.u32.f64 s4, d20", 1,10)
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GEN_TWOVEC_QDS_TEST(vcvtp_u32_f64, "vcvtp.u32.f64 s7, d31", 1,15)
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GEN_TWOVEC_QDS_TEST(vcvtm_u32_f64, "vcvtm.u32.f64 s1, d0", 0,0)
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GEN_TWOVEC_QDS_TEST(vcvtn_u32_f32, "vcvtn.u32.f32 s27, s5", 6,1)
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GEN_TWOVEC_QDS_TEST(vcvta_u32_f32, "vcvta.u32.f32 s4, s20", 1,5)
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GEN_TWOVEC_QDS_TEST(vcvtp_u32_f32, "vcvtp.u32.f32 s7, s31", 1,7)
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GEN_TWOVEC_QDS_TEST(vcvtm_u32_f32, "vcvtm.u32.f32 s1, s0", 0,0)
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GEN_TWOVEC_QDS_TEST(vcvtb_f64_f16, "vcvtb.f64.f16 d27, s18", 13, 4)
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GEN_TWOVEC_QDS_TEST(vcvtt_f64_f16, "vcvtt.f64.f16 d28, s17", 14, 4)
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GEN_TWOVEC_QDS_TEST(vcvtb_f16_f64, "vcvtb.f16.f64 s9, d17", 2, 8)
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GEN_TWOVEC_QDS_TEST(vcvtt_f16_f64, "vcvtt.f16.f64 s8, d27", 2, 13)
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GEN_TWOVEC_QDS_TEST(vrintzeq_f64_f64, "vrintzeq.f64.f64 d0, d9", 0, 4)
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GEN_TWOVEC_QDS_TEST(vrintzne_f64_f64, "vrintzne.f64.f64 d1, d10", 0, 5)
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GEN_TWOVEC_QDS_TEST(vrintzal_f64_f64, "vrintzal.f64.f64 d2, d11", 1, 5)
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GEN_TWOVEC_QDS_TEST(vrintreq_f64_f64, "vrintreq.f64.f64 d3, d12", 1, 6)
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GEN_TWOVEC_QDS_TEST(vrintrne_f64_f64, "vrintrne.f64.f64 d4, d13", 2, 6)
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GEN_TWOVEC_QDS_TEST(vrintral_f64_f64, "vrintral.f64.f64 d5, d14", 2, 7)
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GEN_TWOVEC_QDS_TEST(vrintxeq_f64_f64, "vrintxeq.f64.f64 d6, d15", 3, 7)
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GEN_TWOVEC_QDS_TEST(vrintxne_f64_f64, "vrintxne.f64.f64 d7, d16", 3, 8)
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GEN_TWOVEC_QDS_TEST(vrintxal_f64_f64, "vrintxal.f64.f64 d8, d8", 4, 4)
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GEN_TWOVEC_QDS_TEST(vrintzeq_f32_f32, "vrintzeq.f32.f32 s0, s9", 0, 2)
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GEN_TWOVEC_QDS_TEST(vrintzne_f32_f32, "vrintzne.f32.f32 s1, s10", 0, 2)
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GEN_TWOVEC_QDS_TEST(vrintzal_f32_f32, "vrintzal.f32.f32 s2, s11", 0, 2)
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GEN_TWOVEC_QDS_TEST(vrintreq_f32_f32, "vrintreq.f32.f32 s3, s12", 0, 3)
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GEN_TWOVEC_QDS_TEST(vrintrne_f32_f32, "vrintrne.f32.f32 s4, s13", 1, 3)
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GEN_TWOVEC_QDS_TEST(vrintral_f32_f32, "vrintral.f32.f32 s5, s14", 1, 3)
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GEN_TWOVEC_QDS_TEST(vrintxeq_f32_f32, "vrintxeq.f32.f32 s6, s15", 1, 3)
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GEN_TWOVEC_QDS_TEST(vrintxne_f32_f32, "vrintxne.f32.f32 s7, s16", 1, 4)
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GEN_TWOVEC_QDS_TEST(vrintxal_f32_f32, "vrintxal.f32.f32 s8, s8", 2, 2)
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GEN_TWOVEC_QDS_TEST(vrintn_f64_f64, "vrintn.f64.f64 d3, d15", 1, 7)
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GEN_TWOVEC_QDS_TEST(vrinta_f64_f64, "vrinta.f64.f64 d6, d18", 3, 9)
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GEN_TWOVEC_QDS_TEST(vrintp_f64_f64, "vrintp.f64.f64 d9, d21", 4, 10)
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GEN_TWOVEC_QDS_TEST(vrintm_f64_f64, "vrintm.f64.f64 d12, d12", 6, 6)
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GEN_TWOVEC_QDS_TEST(vrintn_f32_f32, "vrintn.f32.f32 s3, s15", 0, 3)
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GEN_TWOVEC_QDS_TEST(vrinta_f32_f32, "vrinta.f32.f32 s6, s18", 1, 4)
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GEN_TWOVEC_QDS_TEST(vrintp_f32_f32, "vrintp.f32.f32 s9, s21", 2, 5)
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GEN_TWOVEC_QDS_TEST(vrintm_f32_f32, "vrintm.f32.f32 s12, s12", 3, 3)
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GEN_THREEVEC_QDS_TEST(vmaxnm_f32_vec64, "vmaxnm.f32 d15,d16,d20", 7,8,10)
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GEN_THREEVEC_QDS_TEST(vmaxnm_f32_vec128, "vmaxnm.f32 q7, q8, q10", 7,8,10)
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GEN_THREEVEC_QDS_TEST(vminnm_f32_vec64, "vminnm.f32 d15,d16,d20", 7,8,10)
|
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GEN_THREEVEC_QDS_TEST(vminnm_f32_vec128, "vminnm.f32 q7, q8, q10", 7,8,10)
|
||||
|
||||
GEN_TWOVEC_QDS_TEST(vcvtn_s32_f32_vec64, "vcvtn.s32.f32 d0, d20", 0, 10)
|
||||
GEN_TWOVEC_QDS_TEST(vcvta_s32_f32_vec64, "vcvta.s32.f32 d5, d25", 2, 12)
|
||||
GEN_TWOVEC_QDS_TEST(vcvtp_s32_f32_vec64, "vcvtp.s32.f32 d10, d30", 5, 15)
|
||||
GEN_TWOVEC_QDS_TEST(vcvtm_s32_f32_vec64, "vcvtm.s32.f32 d15, d15", 7, 7)
|
||||
|
||||
GEN_TWOVEC_QDS_TEST(vcvtn_s32_f32_vec128, "vcvtn.s32.f32 q15, q0", 15, 0)
|
||||
GEN_TWOVEC_QDS_TEST(vcvta_s32_f32_vec128, "vcvta.s32.f32 q14, q1", 14, 1)
|
||||
GEN_TWOVEC_QDS_TEST(vcvtp_s32_f32_vec128, "vcvtp.s32.f32 q13, q2", 13, 2)
|
||||
GEN_TWOVEC_QDS_TEST(vcvtm_s32_f32_vec128, "vcvtm.s32.f32 q12, q3", 12, 3)
|
||||
|
||||
GEN_TWOVEC_QDS_TEST(vcvtn_u32_f32_vec64, "vcvtn.u32.f32 d0, d20", 0, 10)
|
||||
GEN_TWOVEC_QDS_TEST(vcvta_u32_f32_vec64, "vcvta.u32.f32 d5, d25", 2, 12)
|
||||
GEN_TWOVEC_QDS_TEST(vcvtp_u32_f32_vec64, "vcvtp.u32.f32 d10, d30", 5, 15)
|
||||
GEN_TWOVEC_QDS_TEST(vcvtm_u32_f32_vec64, "vcvtm.u32.f32 d15, d15", 7, 7)
|
||||
|
||||
GEN_TWOVEC_QDS_TEST(vcvtn_u32_f32_vec128, "vcvtn.u32.f32 q15, q0", 15, 0)
|
||||
GEN_TWOVEC_QDS_TEST(vcvta_u32_f32_vec128, "vcvta.u32.f32 q14, q1", 14, 1)
|
||||
GEN_TWOVEC_QDS_TEST(vcvtp_u32_f32_vec128, "vcvtp.u32.f32 q13, q2", 13, 2)
|
||||
GEN_TWOVEC_QDS_TEST(vcvtm_u32_f32_vec128, "vcvtm.u32.f32 q12, q3", 12, 3)
|
||||
|
||||
GEN_TWOVEC_QDS_TEST(vrintn_f32_f32_vec64, "vrintn.f32.f32 d0, d18", 0, 9)
|
||||
GEN_TWOVEC_QDS_TEST(vrinta_f32_f32_vec64, "vrinta.f32.f32 d3, d21", 1, 10)
|
||||
GEN_TWOVEC_QDS_TEST(vrintp_f32_f32_vec64, "vrintp.f32.f32 d6, d24", 3, 12)
|
||||
GEN_TWOVEC_QDS_TEST(vrintm_f32_f32_vec64, "vrintm.f32.f32 d9, d27", 4, 13)
|
||||
GEN_TWOVEC_QDS_TEST(vrintz_f32_f32_vec64, "vrintz.f32.f32 d12, d30", 6, 15)
|
||||
GEN_TWOVEC_QDS_TEST(vrintx_f32_f32_vec64, "vrintx.f32.f32 d15, d15", 7, 7)
|
||||
|
||||
GEN_TWOVEC_QDS_TEST(vrintn_f32_f32_vec128, "vrintn.f32.f32 q0, q2", 0, 2)
|
||||
GEN_TWOVEC_QDS_TEST(vrinta_f32_f32_vec128, "vrinta.f32.f32 q3, q5", 3, 5)
|
||||
GEN_TWOVEC_QDS_TEST(vrintp_f32_f32_vec128, "vrintp.f32.f32 q6, q8", 6, 8)
|
||||
GEN_TWOVEC_QDS_TEST(vrintm_f32_f32_vec128, "vrintm.f32.f32 q9, q11", 9, 11)
|
||||
GEN_TWOVEC_QDS_TEST(vrintz_f32_f32_vec128, "vrintz.f32.f32 q12, q14", 12, 14)
|
||||
GEN_TWOVEC_QDS_TEST(vrintx_f32_f32_vec128, "vrintx.f32.f32 q15, q15", 15, 15)
|
||||
|
||||
int main ( void )
|
||||
{
|
||||
if (1) DO50( test_vselge_f32(TySF) );
|
||||
if (1) DO50( test_vselge_f64(TyDF) );
|
||||
|
||||
if (1) DO50( test_vselgt_f32(TySF) );
|
||||
if (1) DO50( test_vselgt_f64(TyDF) );
|
||||
|
||||
if (1) DO50( test_vseleq_f32(TySF) );
|
||||
if (1) DO50( test_vseleq_f64(TyDF) );
|
||||
|
||||
if (1) DO50( test_vselvs_f32(TySF) );
|
||||
if (1) DO50( test_vselvs_f64(TyDF) );
|
||||
|
||||
if (1) DO50( test_vmaxnm_f32(TySF) );
|
||||
if (1) DO50( test_vmaxnm_f64(TyDF) );
|
||||
|
||||
if (1) DO50( test_vminnm_f32(TySF) );
|
||||
if (1) DO50( test_vminnm_f64(TyDF) );
|
||||
|
||||
if (1) DO50( test_vcvtn_s32_f64(TyDF) );
|
||||
if (1) DO50( test_vcvta_s32_f64(TyDF) );
|
||||
if (1) DO50( test_vcvtp_s32_f64(TyDF) );
|
||||
if (1) DO50( test_vcvtm_s32_f64(TyDF) );
|
||||
|
||||
if (1) DO50( test_vcvtn_s32_f32(TySF) );
|
||||
if (1) DO50( test_vcvta_s32_f32(TySF) );
|
||||
if (1) DO50( test_vcvtp_s32_f32(TySF) );
|
||||
if (1) DO50( test_vcvtm_s32_f32(TySF) );
|
||||
|
||||
if (1) DO50( test_vcvtn_u32_f64(TyDF) );
|
||||
if (1) DO50( test_vcvta_u32_f64(TyDF) );
|
||||
if (1) DO50( test_vcvtp_u32_f64(TyDF) );
|
||||
if (1) DO50( test_vcvtm_u32_f64(TyDF) );
|
||||
|
||||
if (1) DO50( test_vcvtn_u32_f32(TySF) );
|
||||
if (1) DO50( test_vcvta_u32_f32(TySF) );
|
||||
if (1) DO50( test_vcvtp_u32_f32(TySF) );
|
||||
if (1) DO50( test_vcvtm_u32_f32(TySF) );
|
||||
|
||||
if (1) DO50( test_vcvtb_f64_f16(TyDF) );
|
||||
if (1) DO50( test_vcvtt_f64_f16(TyDF) );
|
||||
|
||||
if (1) DO50( test_vcvtb_f16_f64(TyHF) );
|
||||
if (1) DO50( test_vcvtt_f16_f64(TyHF) );
|
||||
|
||||
if (1) DO50( test_vrintzeq_f64_f64(TyDF) );
|
||||
if (1) DO50( test_vrintzne_f64_f64(TyDF) );
|
||||
if (1) DO50( test_vrintzal_f64_f64(TyDF) );
|
||||
|
||||
if (1) DO50( test_vrintreq_f64_f64(TyDF) );
|
||||
if (1) DO50( test_vrintrne_f64_f64(TyDF) );
|
||||
if (1) DO50( test_vrintral_f64_f64(TyDF) );
|
||||
|
||||
if (1) DO50( test_vrintxeq_f64_f64(TyDF) );
|
||||
if (1) DO50( test_vrintxne_f64_f64(TyDF) );
|
||||
if (1) DO50( test_vrintxal_f64_f64(TyDF) );
|
||||
|
||||
if (1) DO50( test_vrintzeq_f32_f32(TySF) );
|
||||
if (1) DO50( test_vrintzne_f32_f32(TySF) );
|
||||
if (1) DO50( test_vrintzal_f32_f32(TySF) );
|
||||
|
||||
if (1) DO50( test_vrintreq_f32_f32(TySF) );
|
||||
if (1) DO50( test_vrintrne_f32_f32(TySF) );
|
||||
if (1) DO50( test_vrintral_f32_f32(TySF) );
|
||||
|
||||
if (1) DO50( test_vrintxeq_f32_f32(TySF) );
|
||||
if (1) DO50( test_vrintxne_f32_f32(TySF) );
|
||||
if (1) DO50( test_vrintxal_f32_f32(TySF) );
|
||||
|
||||
if (1) DO50( test_vrintn_f64_f64(TyDF) );
|
||||
if (1) DO50( test_vrinta_f64_f64(TyDF) );
|
||||
if (1) DO50( test_vrintp_f64_f64(TyDF) );
|
||||
if (1) DO50( test_vrintm_f64_f64(TyDF) );
|
||||
|
||||
if (1) DO50( test_vrintn_f32_f32(TySF) );
|
||||
if (1) DO50( test_vrinta_f32_f32(TySF) );
|
||||
if (1) DO50( test_vrintp_f32_f32(TySF) );
|
||||
if (1) DO50( test_vrintm_f32_f32(TySF) );
|
||||
|
||||
if (1) DO50( test_vmaxnm_f32_vec64(TySF) );
|
||||
if (1) DO50( test_vmaxnm_f32_vec128(TySF) );
|
||||
|
||||
if (1) DO50( test_vminnm_f32_vec64(TySF) );
|
||||
if (1) DO50( test_vminnm_f32_vec128(TySF) );
|
||||
|
||||
if (1) DO50( test_vcvtn_s32_f32_vec64(TySF) );
|
||||
if (1) DO50( test_vcvta_s32_f32_vec64(TySF) );
|
||||
if (1) DO50( test_vcvtp_s32_f32_vec64(TySF) );
|
||||
if (1) DO50( test_vcvtm_s32_f32_vec64(TySF) );
|
||||
|
||||
if (1) DO50( test_vcvtn_s32_f32_vec128(TySF) );
|
||||
if (1) DO50( test_vcvta_s32_f32_vec128(TySF) );
|
||||
if (1) DO50( test_vcvtp_s32_f32_vec128(TySF) );
|
||||
if (1) DO50( test_vcvtm_s32_f32_vec128(TySF) );
|
||||
|
||||
if (1) DO50( test_vcvtn_u32_f32_vec64(TySF) );
|
||||
if (1) DO50( test_vcvta_u32_f32_vec64(TySF) );
|
||||
if (1) DO50( test_vcvtp_u32_f32_vec64(TySF) );
|
||||
if (1) DO50( test_vcvtm_u32_f32_vec64(TySF) );
|
||||
|
||||
if (1) DO50( test_vcvtn_u32_f32_vec128(TySF) );
|
||||
if (1) DO50( test_vcvta_u32_f32_vec128(TySF) );
|
||||
if (1) DO50( test_vcvtp_u32_f32_vec128(TySF) );
|
||||
if (1) DO50( test_vcvtm_u32_f32_vec128(TySF) );
|
||||
|
||||
if (1) DO50( test_vrintn_f32_f32_vec64(TySF) );
|
||||
if (1) DO50( test_vrinta_f32_f32_vec64(TySF) );
|
||||
if (1) DO50( test_vrintp_f32_f32_vec64(TySF) );
|
||||
if (1) DO50( test_vrintm_f32_f32_vec64(TySF) );
|
||||
if (1) DO50( test_vrintz_f32_f32_vec64(TySF) );
|
||||
if (1) DO50( test_vrintx_f32_f32_vec64(TySF) );
|
||||
|
||||
if (1) DO50( test_vrintn_f32_f32_vec128(TySF) );
|
||||
if (1) DO50( test_vrinta_f32_f32_vec128(TySF) );
|
||||
if (1) DO50( test_vrintp_f32_f32_vec128(TySF) );
|
||||
if (1) DO50( test_vrintm_f32_f32_vec128(TySF) );
|
||||
if (1) DO50( test_vrintz_f32_f32_vec128(TySF) );
|
||||
if (1) DO50( test_vrintx_f32_f32_vec128(TySF) );
|
||||
|
||||
return 0;
|
||||
}
|
||||
Loading…
x
Reference in New Issue
Block a user