mirror of
https://github.com/Zenithsiz/ftmemsim-valgrind.git
synced 2026-02-03 18:13:01 +00:00
callgrind/tests/filter_stderr
cachegrind/tests/filter_stderr
Filter out an additional warning, so the tests pass on machines with a
6MB L2 cache.
cachegrind/cg-x86.c
cachegrind/cg-amd64.c
These two files were almost identical. cg-amd64.c now just #includes
cg-x86.c.
git-svn-id: svn://svn.valgrind.org/valgrind/trunk@8912
This commit is contained in:
Nicholas Nethercote
parent
fa7ee0dc5b
commit
2916a0d98f
@ -28,339 +28,7 @@
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The GNU General Public License is contained in the file COPYING.
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*/
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#include "pub_tool_basics.h"
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#include "pub_tool_cpuid.h"
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#include "pub_tool_libcbase.h"
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#include "pub_tool_libcassert.h"
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#include "pub_tool_libcprint.h"
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#include "cg_arch.h"
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// All CPUID info taken from sandpile.org/a32/cpuid.htm */
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// Probably only works for Intel and AMD chips, and probably only for some of
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// them.
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static void micro_ops_warn(Int actual_size, Int used_size, Int line_size)
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{
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VG_(message)(Vg_DebugMsg,
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"warning: Pentium 4 with %d KB micro-op instruction trace cache",
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actual_size);
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VG_(message)(Vg_DebugMsg,
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" Simulating a %d KB I-cache with %d B lines",
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used_size, line_size);
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}
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/* Intel method is truly wretched. We have to do an insane indexing into an
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* array of pre-defined configurations for various parts of the memory
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* hierarchy.
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* According to Intel Processor Identification, App Note 485.
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*/
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static
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Int Intel_cache_info(Int level, cache_t* I1c, cache_t* D1c, cache_t* L2c)
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{
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Int cpuid1_eax;
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Int cpuid1_ignore;
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Int family;
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Int model;
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UChar info[16];
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Int i, trials;
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Bool L2_found = False;
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if (level < 2) {
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VG_(message)(Vg_DebugMsg,
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"warning: CPUID level < 2 for Intel processor (%d)",
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level);
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return -1;
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}
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/* family/model needed to distinguish code reuse (currently 0x49) */
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VG_(cpuid)(1, &cpuid1_eax, &cpuid1_ignore,
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&cpuid1_ignore, &cpuid1_ignore);
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family = (((cpuid1_eax >> 20) & 0xff) << 4) + ((cpuid1_eax >> 8) & 0xf);
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model = (((cpuid1_eax >> 16) & 0xf) << 4) + ((cpuid1_eax >> 4) & 0xf);
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VG_(cpuid)(2, (Int*)&info[0], (Int*)&info[4],
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(Int*)&info[8], (Int*)&info[12]);
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trials = info[0] - 1; /* AL register - bits 0..7 of %eax */
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info[0] = 0x0; /* reset AL */
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if (0 != trials) {
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VG_(message)(Vg_DebugMsg,
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"warning: non-zero CPUID trials for Intel processor (%d)",
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trials);
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return -1;
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}
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for (i = 0; i < 16; i++) {
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switch (info[i]) {
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case 0x0: /* ignore zeros */
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break;
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/* TLB info, ignore */
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case 0x01: case 0x02: case 0x03: case 0x04: case 0x05:
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case 0x4f: case 0x50: case 0x51: case 0x52:
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case 0x56: case 0x57: case 0x59:
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case 0x5b: case 0x5c: case 0x5d:
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case 0xb0: case 0xb1:
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case 0xb3: case 0xb4: case 0xba: case 0xc0:
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break;
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case 0x06: *I1c = (cache_t) { 8, 4, 32 }; break;
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case 0x08: *I1c = (cache_t) { 16, 4, 32 }; break;
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case 0x30: *I1c = (cache_t) { 32, 8, 64 }; break;
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case 0x0a: *D1c = (cache_t) { 8, 2, 32 }; break;
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case 0x0c: *D1c = (cache_t) { 16, 4, 32 }; break;
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case 0x0e:
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/* Real D1 cache configuration is:
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D1c = (cache_t) { 24, 6, 64 }; */
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VG_(message)(Vg_DebugMsg, "warning: 24Kb D1 cache detected, treating as 16Kb");
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*D1c = (cache_t) { 16, 4, 64 };
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break;
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case 0x2c: *D1c = (cache_t) { 32, 8, 64 }; break;
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/* IA-64 info -- panic! */
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case 0x10: case 0x15: case 0x1a:
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case 0x88: case 0x89: case 0x8a: case 0x8d:
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case 0x90: case 0x96: case 0x9b:
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VG_(tool_panic)("IA-64 cache detected?!");
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case 0x22: case 0x23: case 0x25: case 0x29:
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case 0x46: case 0x47: case 0x4a: case 0x4b: case 0x4c: case 0x4d:
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VG_(message)(Vg_DebugMsg,
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"warning: L3 cache detected but ignored");
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break;
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/* These are sectored, whatever that means */
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case 0x39: *L2c = (cache_t) { 128, 4, 64 }; L2_found = True; break;
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case 0x3c: *L2c = (cache_t) { 256, 4, 64 }; L2_found = True; break;
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/* If a P6 core, this means "no L2 cache".
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If a P4 core, this means "no L3 cache".
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We don't know what core it is, so don't issue a warning. To detect
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a missing L2 cache, we use 'L2_found'. */
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case 0x40:
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break;
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case 0x41: *L2c = (cache_t) { 128, 4, 32 }; L2_found = True; break;
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case 0x42: *L2c = (cache_t) { 256, 4, 32 }; L2_found = True; break;
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case 0x43: *L2c = (cache_t) { 512, 4, 32 }; L2_found = True; break;
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case 0x44: *L2c = (cache_t) { 1024, 4, 32 }; L2_found = True; break;
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case 0x45: *L2c = (cache_t) { 2048, 4, 32 }; L2_found = True; break;
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case 0x48:
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/* Real L2 cache configuration is:
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*L2c = (cache_t) { 3072, 12, 64 }; L2_found = True; */
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VG_(message)(Vg_DebugMsg, "warning: 3Mb L2 cache detected, treating as 2Mb");
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*L2c = (cache_t) { 2048, 8, 64 }; L2_found = True;
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break;
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case 0x49:
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if ((family == 15) && (model == 6))
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/* On Xeon MP (family F, model 6), this is for L3 */
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VG_(message)(Vg_DebugMsg,
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"warning: L3 cache detected but ignored");
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else
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*L2c = (cache_t) { 4096, 16, 64 }; L2_found = True;
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break;
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case 0x4e:
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/* Real L2 cache configuration is:
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*L2c = (cache_t) { 6144, 24, 64 }; L2_found = True; */
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VG_(message)(Vg_DebugMsg, "warning: 6Mb L2 cache detected, treating as 4Mb");
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*L2c = (cache_t) { 4096, 16, 64 }; L2_found = True;
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break;
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/* These are sectored, whatever that means */
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case 0x60: *D1c = (cache_t) { 16, 8, 64 }; break; /* sectored */
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case 0x66: *D1c = (cache_t) { 8, 4, 64 }; break; /* sectored */
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case 0x67: *D1c = (cache_t) { 16, 4, 64 }; break; /* sectored */
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case 0x68: *D1c = (cache_t) { 32, 4, 64 }; break; /* sectored */
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/* HACK ALERT: Instruction trace cache -- capacity is micro-ops based.
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* conversion to byte size is a total guess; treat the 12K and 16K
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* cases the same since the cache byte size must be a power of two for
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* everything to work!. Also guessing 32 bytes for the line size...
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*/
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case 0x70: /* 12K micro-ops, 8-way */
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*I1c = (cache_t) { 16, 8, 32 };
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micro_ops_warn(12, 16, 32);
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break;
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case 0x71: /* 16K micro-ops, 8-way */
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*I1c = (cache_t) { 16, 8, 32 };
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micro_ops_warn(16, 16, 32);
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break;
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case 0x72: /* 32K micro-ops, 8-way */
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*I1c = (cache_t) { 32, 8, 32 };
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micro_ops_warn(32, 32, 32);
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break;
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/* These are sectored, whatever that means */
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case 0x79: *L2c = (cache_t) { 128, 8, 64 }; L2_found = True; break;
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case 0x7a: *L2c = (cache_t) { 256, 8, 64 }; L2_found = True; break;
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case 0x7b: *L2c = (cache_t) { 512, 8, 64 }; L2_found = True; break;
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case 0x7c: *L2c = (cache_t) { 1024, 8, 64 }; L2_found = True; break;
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case 0x7d: *L2c = (cache_t) { 2048, 8, 64 }; L2_found = True; break;
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case 0x7e: *L2c = (cache_t) { 256, 8, 128 }; L2_found = True; break;
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case 0x7f: *L2c = (cache_t) { 512, 2, 64 }; L2_found = True; break;
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case 0x80: *L2c = (cache_t) { 512, 8, 64 }; L2_found = True; break;
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case 0x81: *L2c = (cache_t) { 128, 8, 32 }; L2_found = True; break;
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case 0x82: *L2c = (cache_t) { 256, 8, 32 }; L2_found = True; break;
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case 0x83: *L2c = (cache_t) { 512, 8, 32 }; L2_found = True; break;
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case 0x84: *L2c = (cache_t) { 1024, 8, 32 }; L2_found = True; break;
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case 0x85: *L2c = (cache_t) { 2048, 8, 32 }; L2_found = True; break;
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case 0x86: *L2c = (cache_t) { 512, 4, 64 }; L2_found = True; break;
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case 0x87: *L2c = (cache_t) { 1024, 8, 64 }; L2_found = True; break;
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/* Ignore prefetch information */
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case 0xf0: case 0xf1:
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break;
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default:
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VG_(message)(Vg_DebugMsg,
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"warning: Unknown Intel cache config value "
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"(0x%x), ignoring", info[i]);
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break;
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}
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}
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if (!L2_found)
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VG_(message)(Vg_DebugMsg,
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"warning: L2 cache not installed, ignore L2 results.");
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return 0;
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}
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/* AMD method is straightforward, just extract appropriate bits from the
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* result registers.
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*
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* Bits, for D1 and I1:
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* 31..24 data L1 cache size in KBs
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* 23..16 data L1 cache associativity (FFh=full)
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* 15.. 8 data L1 cache lines per tag
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* 7.. 0 data L1 cache line size in bytes
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*
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* Bits, for L2:
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* 31..16 unified L2 cache size in KBs
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* 15..12 unified L2 cache associativity (0=off, FFh=full)
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* 11.. 8 unified L2 cache lines per tag
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* 7.. 0 unified L2 cache line size in bytes
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*
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* #3 The AMD K7 processor's L2 cache must be configured prior to relying
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* upon this information. (Whatever that means -- njn)
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*
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* Also, according to Cyrille Chepelov, Duron stepping A0 processors (model
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* 0x630) have a bug and misreport their L2 size as 1KB (it's really 64KB),
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* so we detect that.
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*
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* Returns 0 on success, non-zero on failure.
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*/
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static
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Int AMD_cache_info(cache_t* I1c, cache_t* D1c, cache_t* L2c)
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{
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UInt ext_level;
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UInt dummy, model;
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UInt I1i, D1i, L2i;
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VG_(cpuid)(0x80000000, &ext_level, &dummy, &dummy, &dummy);
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if (0 == (ext_level & 0x80000000) || ext_level < 0x80000006) {
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VG_(message)(Vg_UserMsg,
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"warning: ext_level < 0x80000006 for AMD processor (0x%x)",
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ext_level);
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return -1;
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}
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VG_(cpuid)(0x80000005, &dummy, &dummy, &D1i, &I1i);
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VG_(cpuid)(0x80000006, &dummy, &dummy, &L2i, &dummy);
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VG_(cpuid)(0x1, &model, &dummy, &dummy, &dummy);
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/* Check for Duron bug */
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if (model == 0x630) {
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VG_(message)(Vg_UserMsg,
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"Buggy Duron stepping A0. Assuming L2 size=65536 bytes");
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L2i = (64 << 16) | (L2i & 0xffff);
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}
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D1c->size = (D1i >> 24) & 0xff;
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D1c->assoc = (D1i >> 16) & 0xff;
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D1c->line_size = (D1i >> 0) & 0xff;
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I1c->size = (I1i >> 24) & 0xff;
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I1c->assoc = (I1i >> 16) & 0xff;
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I1c->line_size = (I1i >> 0) & 0xff;
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L2c->size = (L2i >> 16) & 0xffff; /* Nb: different bits used for L2 */
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L2c->assoc = (L2i >> 12) & 0xf;
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L2c->line_size = (L2i >> 0) & 0xff;
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return 0;
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}
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static
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Int get_caches_from_CPUID(cache_t* I1c, cache_t* D1c, cache_t* L2c)
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{
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Int level, ret;
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Char vendor_id[13];
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if (!VG_(has_cpuid)()) {
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VG_(message)(Vg_DebugMsg, "CPUID instruction not supported");
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return -1;
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}
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VG_(cpuid)(0, &level, (int*)&vendor_id[0],
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(int*)&vendor_id[8], (int*)&vendor_id[4]);
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vendor_id[12] = '\0';
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if (0 == level) {
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VG_(message)(Vg_DebugMsg, "CPUID level is 0, early Pentium?");
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return -1;
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}
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/* Only handling Intel and AMD chips... no Cyrix, Transmeta, etc */
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if (0 == VG_(strcmp)(vendor_id, "GenuineIntel")) {
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ret = Intel_cache_info(level, I1c, D1c, L2c);
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} else if (0 == VG_(strcmp)(vendor_id, "AuthenticAMD")) {
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ret = AMD_cache_info(I1c, D1c, L2c);
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} else {
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VG_(message)(Vg_DebugMsg, "CPU vendor ID not recognised (%s)",
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vendor_id);
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return -1;
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}
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/* Successful! Convert sizes from KB to bytes */
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I1c->size *= 1024;
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D1c->size *= 1024;
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L2c->size *= 1024;
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return ret;
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}
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void VG_(configure_caches)(cache_t* I1c, cache_t* D1c, cache_t* L2c,
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Bool all_caches_clo_defined)
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{
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Int res;
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// Set caches to default.
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*I1c = (cache_t) { 65536, 2, 64 };
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*D1c = (cache_t) { 65536, 2, 64 };
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*L2c = (cache_t) { 262144, 8, 64 };
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// Then replace with any info we can get from CPUID.
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res = get_caches_from_CPUID(I1c, D1c, L2c);
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// Warn if CPUID failed and config not completely specified from cmd line.
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if (res != 0 && !all_caches_clo_defined) {
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VG_(message)(Vg_DebugMsg,
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"Warning: Couldn't auto-detect cache config, using one "
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"or more defaults ");
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}
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}
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#include "cg-x86.c"
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/*--------------------------------------------------------------------*/
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/*--- end ---*/
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@ -1,6 +1,6 @@
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/*--------------------------------------------------------------------*/
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/*--- x86-specific definitions. cg-x86.c ---*/
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/*--- x86-specific (and AMD64-specific) definitions. cg-x86.c ---*/
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/*--------------------------------------------------------------------*/
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/*
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@ -17,4 +17,5 @@ sed "s/\(\(I1\|D1\|L2\|L2i\|L2d\) *\(misses\|miss rate\):\)[ 0-9,()+rdw%\.]*$/\1
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sed "/warning: Pentium 4 with 12 KB micro-op instruction trace cache/d" |
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sed "/Simulating a 16 KB I-cache with 32 B lines/d" |
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sed "/warning: L3 cache detected but ignored/d" |
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sed "/warning: 6Mb L2 cache detected, treating as 4Mb/d" |
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sed "/Warning: Cannot auto-detect cache config on PPC.., using one or more defaults/d"
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@ -23,4 +23,5 @@ sed "s/\(\(I1\|D1\|L2\|L2i\|L2d\) *\(misses\|miss rate\):\)[ 0-9,()+rdw%\.]*$/\1
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sed "/warning: Pentium 4 with 12 KB micro-op instruction trace cache/d" |
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sed "/Simulating a 16 KB I-cache with 32 B lines/d" |
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sed "/warning: L3 cache detected but ignored/d" |
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sed "/warning: 6Mb L2 cache detected, treating as 4Mb/d" |
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sed "/Warning: Cannot auto-detect cache config on PPC.., using one or more defaults/d"
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