diff --git a/configure.in b/configure.in index 6ac32b041..5cf28a175 100644 --- a/configure.in +++ b/configure.in @@ -1771,6 +1771,28 @@ if test x$ac_have_as_ppc_mftocrf = xyes ; then fi +# does the ppc assembler support "lfdp" and other phased out floating point insns? +AC_MSG_CHECKING([if ppc32/64 asm supports phased out floating point instructions]) + +AC_COMPILE_IFELSE([AC_LANG_PROGRAM([[]], [[ + do { typedef struct { + double hi; + double lo; + } dbl_pair_t; + dbl_pair_t dbl_pair[3]; + __asm__ volatile ("lfdp 10, %0"::"m" (dbl_pair[0])); + } while (0) +]])], [ +ac_have_as_ppc_fpPO=yes +AC_MSG_RESULT([yes]) +], [ +ac_have_as_ppc_fpPO=no +AC_MSG_RESULT([no]) +]) +if test x$ac_have_as_ppc_fpPO = xyes ; then + AC_DEFINE(HAVE_AS_PPC_FPPO, 1, [Define to 1 if as supports floating point phased out category.]) +fi + CFLAGS=$safe_CFLAGS # does the x86/amd64 assembler understand SSE3 instructions? diff --git a/memcheck/tests/ppc32/Makefile.am b/memcheck/tests/ppc32/Makefile.am index 40033fc31..bd70eea67 100644 --- a/memcheck/tests/ppc32/Makefile.am +++ b/memcheck/tests/ppc32/Makefile.am @@ -4,7 +4,8 @@ include $(top_srcdir)/Makefile.tool-tests.am dist_noinst_SCRIPTS = filter_stderr EXTRA_DIST = $(noinst_SCRIPTS) \ - power_ISA2_05.stderr.exp power_ISA2_05.stdout.exp power_ISA2_05.vgtest + power_ISA2_05.stderr.exp power_ISA2_05.stdout.exp power_ISA2_05.vgtest \ + power_ISA2_05.stdout.exp_Without_FPPO check_PROGRAMS = \ power_ISA2_05 diff --git a/memcheck/tests/ppc32/power_ISA2_05.c b/memcheck/tests/ppc32/power_ISA2_05.c index 017845261..3736c274a 100644 --- a/memcheck/tests/ppc32/power_ISA2_05.c +++ b/memcheck/tests/ppc32/power_ISA2_05.c @@ -1,4 +1,5 @@ #include +#include double foo = -1.0; double FRT1; @@ -65,9 +66,15 @@ void test_lfiwax() ** FPp = leftmost 64 bits stored at DS(RA) ** FPp+1= rightmost 64 bits stored at DS(RA) ** FPp must be an even float register +** +** The [st|l]fdp[x] instructions were put into the "Floating-Point.Phased-Out" +** category in ISA 2.06 (i.e., POWER7 timeframe). If valgrind and its +** testsuite are built with -mcpu=power7 (or later), then the assembler will +** not recognize those phased out instructions. */ void test_double_pair_instrs() { +#ifdef HAVE_AS_PPC_FPPO typedef struct { double hi; double lo; @@ -122,6 +129,7 @@ void test_double_pair_instrs() __asm__ volatile ("stfdpx 10, 20, 21"); printf("stfdpx (%f, %f) => F_hi=%f, F_lo=%f\n", FRT1, FRT2, dbl_pair[2].hi, dbl_pair[2].lo); +#endif } diff --git a/memcheck/tests/ppc32/power_ISA2_05.stdout.exp_Without_FPPO b/memcheck/tests/ppc32/power_ISA2_05.stdout.exp_Without_FPPO new file mode 120000 index 000000000..da5c10925 --- /dev/null +++ b/memcheck/tests/ppc32/power_ISA2_05.stdout.exp_Without_FPPO @@ -0,0 +1 @@ +../ppc64/power_ISA2_05.stdout.exp_Without_FPPO \ No newline at end of file diff --git a/memcheck/tests/ppc64/Makefile.am b/memcheck/tests/ppc64/Makefile.am index a18afd76f..96eb5760f 100644 --- a/memcheck/tests/ppc64/Makefile.am +++ b/memcheck/tests/ppc64/Makefile.am @@ -4,7 +4,8 @@ include $(top_srcdir)/Makefile.tool-tests.am dist_noinst_SCRIPTS = filter_stderr EXTRA_DIST = $(noinst_SCRIPTS) \ - power_ISA2_05.stderr.exp power_ISA2_05.stdout.exp power_ISA2_05.vgtest + power_ISA2_05.stderr.exp power_ISA2_05.stdout.exp power_ISA2_05.vgtest \ + power_ISA2_05.stdout.exp_Without_FPPO check_PROGRAMS = \ power_ISA2_05 diff --git a/memcheck/tests/ppc64/power_ISA2_05.c b/memcheck/tests/ppc64/power_ISA2_05.c index 8c0eab99a..f552dc421 100644 --- a/memcheck/tests/ppc64/power_ISA2_05.c +++ b/memcheck/tests/ppc64/power_ISA2_05.c @@ -1,4 +1,5 @@ #include +#include double foo = -1.0; double FRT1; @@ -63,9 +64,16 @@ void test_lfiwax() ** FPp = leftmost 64 bits stored at DS(RA) ** FPp+1= rightmost 64 bits stored at DS(RA) ** FPp must be an even float register +** +** The [st|l]fdp[x] instructions were put into the "Floating-Point.Phased-Out" +** category in ISA 2.06 (i.e., POWER7 timeframe). If valgrind and its +** testsuite are built with -mcpu=power7 (or later), then the assembler will +** not recognize those phased out instructions. +** */ void test_double_pair_instrs() { +#ifdef HAVE_AS_PPC_FPPO typedef struct { double hi; double lo; @@ -120,6 +128,7 @@ void test_double_pair_instrs() __asm__ volatile ("stfdpx 10, 20, 21"); printf("stfdpx (%f, %f) => F_hi=%f, F_lo=%f\n", FRT1, FRT2, dbl_pair[2].hi, dbl_pair[2].lo); +#endif } diff --git a/memcheck/tests/ppc64/power_ISA2_05.stdout.exp_Without_FPPO b/memcheck/tests/ppc64/power_ISA2_05.stdout.exp_Without_FPPO new file mode 100644 index 000000000..19455263a --- /dev/null +++ b/memcheck/tests/ppc64/power_ISA2_05.stdout.exp_Without_FPPO @@ -0,0 +1,119 @@ +lwarx => 0 +ldarx => bad0beef +fcpsgn sign=10.101010, base=11.111111 => 11.111111 +fcpsgn sign=10.101010, base=-0.000000 => 0.000000 +fcpsgn sign=10.101010, base=0.000000 => 0.000000 +fcpsgn sign=10.101010, base=-11.111111 => 11.111111 +fcpsgn sign=-0.000000, base=11.111111 => -11.111111 +fcpsgn sign=-0.000000, base=-0.000000 => -0.000000 +fcpsgn sign=-0.000000, base=0.000000 => -0.000000 +fcpsgn sign=-0.000000, base=-11.111111 => -11.111111 +fcpsgn sign=0.000000, base=11.111111 => 11.111111 +fcpsgn sign=0.000000, base=-0.000000 => 0.000000 +fcpsgn sign=0.000000, base=0.000000 => 0.000000 +fcpsgn sign=0.000000, base=-11.111111 => 11.111111 +fcpsgn sign=-10.101010, base=11.111111 => -11.111111 +fcpsgn sign=-10.101010, base=-0.000000 => -0.000000 +fcpsgn sign=-10.101010, base=0.000000 => -0.000000 +fcpsgn sign=-10.101010, base=-11.111111 => -11.111111 +lfiwax (-1024.000000) => FRT=(ffffffff, c0900000) +prtyd (0) => parity=0 +prtyw (0) => parity=0 +prtyd (1) => parity=1 +prtyw (1) => parity=1 +prtyd (2) => parity=0 +prtyw (2) => parity=0 +prtyd (3) => parity=1 +prtyw (3) => parity=1 +prtyd (4) => parity=0 +prtyw (4) => parity=0 +prtyd (5) => parity=1 +prtyw (5) => parity=1 +prtyd (6) => parity=0 +prtyw (6) => parity=0 +prtyd (7) => parity=1 +prtyw (7) => parity=1 +prtyd (8) => parity=0 +prtyw (8) => parity=0 +prtyd (9) => parity=1 +prtyw (9) => parity=1 +prtyd (a) => parity=0 +prtyw (a) => parity=0 +prtyd (b) => parity=1 +prtyw (b) => parity=1 +prtyd (c) => parity=0 +prtyw (c) => parity=0 +prtyd (d) => parity=1 +prtyw (d) => parity=1 +prtyd (e) => parity=0 +prtyw (e) => parity=0 +prtyd (f) => parity=1 +prtyw (f) => parity=1 +prtyd (10) => parity=0 +prtyw (10) => parity=0 +prtyd (11) => parity=1 +prtyw (11) => parity=1 +prtyd (12) => parity=0 +prtyw (12) => parity=0 +prtyd (13) => parity=1 +prtyw (13) => parity=1 +prtyd (14) => parity=0 +prtyw (14) => parity=0 +prtyd (15) => parity=1 +prtyw (15) => parity=1 +prtyd (16) => parity=0 +prtyw (16) => parity=0 +prtyd (17) => parity=1 +prtyw (17) => parity=1 +prtyd (18) => parity=0 +prtyw (18) => parity=0 +prtyd (19) => parity=1 +prtyw (19) => parity=1 +prtyd (1a) => parity=0 +prtyw (1a) => parity=0 +prtyd (1b) => parity=1 +prtyw (1b) => parity=1 +prtyd (1c) => parity=0 +prtyw (1c) => parity=0 +prtyd (1d) => parity=1 +prtyw (1d) => parity=1 +prtyd (1e) => parity=0 +prtyw (1e) => parity=0 +prtyd (1f) => parity=1 +prtyw (1f) => parity=1 +prtyd (20) => parity=0 +prtyw (20) => parity=0 +prtyd (21) => parity=1 +prtyw (21) => parity=1 +prtyd (22) => parity=0 +prtyw (22) => parity=0 +prtyd (23) => parity=1 +prtyw (23) => parity=1 +prtyd (24) => parity=0 +prtyw (24) => parity=0 +prtyd (25) => parity=1 +prtyw (25) => parity=1 +prtyd (26) => parity=0 +prtyw (26) => parity=0 +prtyd (27) => parity=1 +prtyw (27) => parity=1 +prtyd (28) => parity=0 +prtyw (28) => parity=0 +prtyd (29) => parity=1 +prtyw (29) => parity=1 +prtyd (2a) => parity=0 +prtyw (2a) => parity=0 +prtyd (2b) => parity=1 +prtyw (2b) => parity=1 +prtyd (2c) => parity=0 +prtyw (2c) => parity=0 +prtyd (2d) => parity=1 +prtyw (2d) => parity=1 +prtyd (2e) => parity=0 +prtyw (2e) => parity=0 +prtyd (2f) => parity=1 +prtyw (2f) => parity=1 +prtyd (30) => parity=0 +prtyw (30) => parity=0 +prtyd (31) => parity=1 +prtyw (31) => parity=1