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https://github.com/Zenithsiz/ftmemsim-valgrind.git
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PowerPC:, Fix test test_isa_3_1_R1_RT.c, test_isa_3_1_R1_XT.c
Test adds a block of xori instructions for use with the PC relative tests. The registers used by the xori instructions need to be saved and restored, otherwise the register changes can impact the execution of the for loops in the test as registers are randomly changed. The issue occcurs when GCC is optimizing and inlining the test functions.
This commit is contained in:
Carl Love
parent
04054f36be
commit
20cc0680c3
@ -46,4 +46,3 @@ extern unsigned long get_vsrhd_vs26();
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extern unsigned long get_vsrhd_vs27();
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extern unsigned long get_vsrhd_vs28();
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extern unsigned long get_vsrhd_vs29();
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@ -49,108 +49,304 @@ struct test_list_t current_test;
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#include "isa_3_1_helpers.h"
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#ifdef __powerpc64__
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typedef uint64_t HWord_t;
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/* Save and restore all of the registers but rt which is the result of the instruction
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under test. Need to ensure the PAD_ORI does not change the other registers. This
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really shouldn't be needed but the optimization gets messed up when it inlines the
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test function. */
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#define SAVE_REGS(addr) \
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asm volatile( \
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" std 21, 0(%0) \n" \
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" std 22, 8(%0) \n" \
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" std 23, 16(%0) \n" \
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" std 24, 24(%0) \n" \
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" std 25, 32(%0) \n" \
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" std 28, 56(%0) \n" \
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" std 29, 64(%0) \n" \
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" std 30, 72(%0) \n" \
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" std 31, 80(%0) \n" \
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::"b"(addr))
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#define SAVE_REG_RT(addr) \
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asm volatile( \
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" std 26, 40(%0) \n" \
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::"b"(addr))
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#define SAVE_REG_27(addr) \
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asm volatile( \
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" std 27, 40(%0) \n" \
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::"b"(addr))
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#define RESTORE_REGS(addr) \
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asm volatile( \
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" ld 21, 0(%0) \n" \
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" ld 22, 8(%0) \n" \
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" ld 23, 16(%0) \n" \
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" ld 24, 24(%0) \n" \
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" ld 25, 32(%0) \n" \
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" ld 28, 56(%0) \n" \
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" ld 29, 64(%0) \n" \
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" ld 30, 72(%0) \n" \
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" ld 31, 80(%0) \n" \
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::"b"(addr))
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#define RESTORE_REG_RT(addr) \
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asm volatile( \
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" ld 26, 40(%0) \n" \
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::"b"(addr))
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#define RESTORE_REG_27(addr) \
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asm volatile( \
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" ld 27, 40(%0) \n" \
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::"b"(addr))
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#else /* !__powerpc64__ */
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typedef uint32_t HWord_t;
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#define SAVE_REGS(addr) \
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asm volatile( \
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" stw 21, 0(%0) \n" \
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" stw 22, 4(%0) \n" \
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" stw 23, 8(%0) \n" \
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" stw 24, 12(%0) \n" \
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" stw 25, 16(%0) \n" \
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" stw 28, 28(%0) \n" \
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" stw 29, 32(%0) \n" \
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" stw 30, 36(%0) \n" \
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" stw 31, 40(%0) \n" \
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::"b"(addr))
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#define SAVE_REG_RT(addr) \
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asm volatile( \
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" stw 26, 20(%0) \n" \
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::"b"(addr))
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#define SAVE_REG_27(addr) \
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asm volatile( \
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" stw 27, 20(%0) \n" \
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::"b"(addr))
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#define RESTORE_REGS(addr) \
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asm volatile( \
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" lwz 21, 0(%0) \n" \
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" lwz 22, 4(%0) \n" \
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" lwz 23, 8(%0) \n" \
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" lwz 24, 12(%0) \n" \
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" lwz 25, 16(%0) \n" \
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" lwz 28, 28(%0) \n" \
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" lwz 29, 32(%0) \n" \
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" lwz 30, 36(%0) \n" \
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" lwz 31, 400(%0) \n" \
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::"b"(addr))
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#define RESTORE_REG_RT(addr) \
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asm volatile( \
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" lwz 26, 40(%0) \n" \
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::"b"(addr))
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#define RESTORE_REG_27(addr) \
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asm volatile( \
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" lwz 27, 40(%0) \n" \
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::"b"(addr))
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#endif /* __powerpc64__ */
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#define NUM_ENTRIES_SAVE_RESTORE 11
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HWord_t temp[NUM_ENTRIES_SAVE_RESTORE];
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static void test_plxvp_off0_R1 (void) {
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SAVE_REGS(temp);
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SAVE_REG_RT(temp);
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SAVE_REG_27(temp);
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PAD_ORI
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__asm__ __volatile__ ("plxvp 20, +0(0),1" );
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PAD_ORI
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RESTORE_REGS(temp);
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RESTORE_REG_RT(temp);
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RESTORE_REG_27(temp);
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}
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static void test_plxvp_off8_R1 (void) {
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SAVE_REGS(temp);
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SAVE_REG_RT(temp);
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SAVE_REG_27(temp);
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PAD_ORI
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__asm__ __volatile__ ("plxvp 20, +8(0),1" );
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PAD_ORI
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RESTORE_REGS(temp);
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RESTORE_REG_RT(temp);
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RESTORE_REG_27(temp);
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}
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static void test_plxvp_off16_R1 (void) {
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SAVE_REGS(temp);
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SAVE_REG_RT(temp);
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SAVE_REG_27(temp);
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PAD_ORI
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__asm__ __volatile__ ("plxvp 20, +16(0),1" );
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PAD_ORI
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RESTORE_REGS(temp);
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RESTORE_REG_RT(temp);
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RESTORE_REG_27(temp);
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}
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static void test_plxvp_off24_R1 (void) {
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SAVE_REGS(temp);
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SAVE_REG_RT(temp);
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SAVE_REG_27(temp);
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PAD_ORI
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__asm__ __volatile__ ("plxvp 20, +24(0),1" );
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PAD_ORI
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RESTORE_REGS(temp);
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RESTORE_REG_RT(temp);
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RESTORE_REG_27(temp);
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}
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static void test_plxvp_off32_R1 (void) {
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SAVE_REGS(temp);
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SAVE_REG_RT(temp);
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SAVE_REG_27(temp);
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PAD_ORI
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__asm__ __volatile__ ("plxvp 20, +32(0),1" );
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PAD_ORI
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RESTORE_REGS(temp);
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RESTORE_REG_RT(temp);
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RESTORE_REG_27(temp);
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}
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static void test_plbz_off0_R1 (void) {
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PAD_ORI
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SAVE_REGS(temp);
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SAVE_REG_27(temp);
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PAD_ORI
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__asm__ __volatile__ ("plbz %0, +0(0), 1" : "=r" (rt) );
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PAD_ORI
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RESTORE_REGS(temp);
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RESTORE_REG_27(temp);
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}
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static void test_plbz_off8_R1 (void) {
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SAVE_REGS(temp);
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SAVE_REG_27(temp);
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PAD_ORI
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__asm__ __volatile__ ("plbz %0, +8(0), 1" : "=r" (rt) );
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PAD_ORI
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RESTORE_REGS(temp);
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RESTORE_REG_27(temp);
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}
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static void test_plbz_off16_R1 (void) {
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SAVE_REGS(temp);
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SAVE_REG_27(temp);
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PAD_ORI
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__asm__ __volatile__ ("plbz %0, +16(0), 1" : "=r" (rt) );
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PAD_ORI
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RESTORE_REGS(temp);
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RESTORE_REG_27(temp);
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}
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static void test_plbz_off32_R1 (void) {
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SAVE_REGS(temp);
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SAVE_REG_27(temp);
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PAD_ORI
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__asm__ __volatile__ ("plbz %0, +32(0), 1" : "=r" (rt) );
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PAD_ORI
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RESTORE_REGS(temp);
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RESTORE_REG_27(temp);
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}
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static void test_plbz_off64_R1 (void) {
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SAVE_REGS(temp);
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SAVE_REG_27(temp);
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PAD_ORI
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__asm__ __volatile__ ("plbz %0, +64(0), 1" : "=r" (rt) );
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PAD_ORI
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PAD_ORI
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RESTORE_REGS(temp);
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RESTORE_REG_27(temp);
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}
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static void test_plhz_off0_R1 (void) {
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SAVE_REGS(temp);
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SAVE_REG_27(temp);
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PAD_ORI
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__asm__ __volatile__ ("plhz %0, +0(0), 1" : "=r" (rt) );
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PAD_ORI
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RESTORE_REGS(temp);
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RESTORE_REG_27(temp);
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}
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static void test_plhz_off8_R1 (void) {
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SAVE_REGS(temp);
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SAVE_REG_27(temp);
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PAD_ORI
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__asm__ __volatile__ ("plhz %0, +8(0), 1" : "=r" (rt) );
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PAD_ORI
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RESTORE_REGS(temp);
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RESTORE_REG_27(temp);
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}
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static void test_plhz_off16_R1 (void) {
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SAVE_REGS(temp);
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SAVE_REG_27(temp);
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PAD_ORI
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__asm__ __volatile__ ("plhz %0, +16(0), 1" : "=r" (rt) );
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PAD_ORI
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RESTORE_REGS(temp);
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RESTORE_REG_27(temp);
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}
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static void test_plhz_off32_R1 (void) {
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SAVE_REGS(temp);
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SAVE_REG_27(temp);
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PAD_ORI
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__asm__ __volatile__ ("plhz %0, +32(0), 1" : "=r" (rt) );
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PAD_ORI
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RESTORE_REGS(temp);
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RESTORE_REG_27(temp);
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}
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static void test_plhz_off64_R1 (void) {
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SAVE_REGS(temp);
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SAVE_REG_27(temp);
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PAD_ORI
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__asm__ __volatile__ ("plhz %0, +64(0), 1" : "=r" (rt) );
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PAD_ORI
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PAD_ORI
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RESTORE_REGS(temp);
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RESTORE_REG_27(temp);
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}
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static void test_plha_off0_R1 (void) {
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SAVE_REGS(temp);
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SAVE_REG_27(temp);
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PAD_ORI
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__asm__ __volatile__ ("plha %0, +0(0), 1" : "=r" (rt) );
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PAD_ORI
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RESTORE_REGS(temp);
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RESTORE_REG_27(temp);
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}
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static void test_plha_off8_R1 (void) {
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SAVE_REGS(temp);
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SAVE_REG_27(temp);
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PAD_ORI
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__asm__ __volatile__ ("plha %0, +8(0), 1" : "=r" (rt) );
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PAD_ORI
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RESTORE_REGS(temp);
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RESTORE_REG_27(temp);
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}
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static void test_plha_off16_R1 (void) {
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SAVE_REGS(temp);
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SAVE_REG_27(temp);
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PAD_ORI
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__asm__ __volatile__ ("plha %0, +16(0), 1" : "=r" (rt) );
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PAD_ORI
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RESTORE_REGS(temp);
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RESTORE_REG_27(temp);
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}
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static void test_plha_off32_R1 (void) {
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SAVE_REGS(temp);
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SAVE_REG_27(temp);
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PAD_ORI
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__asm__ __volatile__ ("plha %0, +32(0), 1" : "=r" (rt) );
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PAD_ORI
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RESTORE_REGS(temp);
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RESTORE_REG_27(temp);
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}
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static void test_plha_off64_R1 (void) {
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SAVE_REGS(temp);
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SAVE_REG_27(temp);
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PAD_ORI
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__asm__ __volatile__ ("plha %0, +64(0), 1" : "=r" (rt) );
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PAD_ORI
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PAD_ORI
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RESTORE_REG_27(temp);
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RESTORE_REGS(temp);
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}
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static void test_plwz_off0_R1 (void) {
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__asm__ __volatile__ ("plwz %0, +0(0), 1" : "=r" (rt) );
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@ -162,15 +358,23 @@ static void test_plwz_off16_R1 (void) {
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__asm__ __volatile__ ("plwz %0, +16(0), 1" : "=r" (rt) );
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}
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static void test_plwz_off32_R1 (void) {
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SAVE_REGS(temp);
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SAVE_REG_27(temp);
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PAD_ORI
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__asm__ __volatile__ ("plwz %0, +32(0), 1" : "=r" (rt) );
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PAD_ORI
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RESTORE_REGS(temp);
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RESTORE_REG_27(temp);
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}
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static void test_plwz_off64_R1 (void) {
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SAVE_REGS(temp);
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SAVE_REG_27(temp);
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PAD_ORI
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__asm__ __volatile__ ("plwz %0, +64(0), 1" : "=r" (rt) );
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PAD_ORI
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PAD_ORI
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RESTORE_REGS(temp);
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RESTORE_REG_27(temp);
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}
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static void test_plwa_off0_R1 (void) {
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__asm__ __volatile__ ("plwa %0, +0(0), 1" : "=r" (rt) );
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@ -182,37 +386,69 @@ static void test_plwa_off16_R1 (void) {
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__asm__ __volatile__ ("plwa %0, +16(0), 1" : "=r" (rt) );
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}
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static void test_plwa_off32_R1 (void) {
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SAVE_REGS(temp);
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SAVE_REG_27(temp);
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PAD_ORI
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__asm__ __volatile__ ("plwa %0, +32(0), 1" : "=r" (rt) );
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PAD_ORI
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RESTORE_REGS(temp);
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RESTORE_REG_27(temp);
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}
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static void test_plwa_off64_R1 (void) {
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SAVE_REGS(temp);
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SAVE_REG_27(temp);
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PAD_ORI
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__asm__ __volatile__ ("plwa %0, +64(0), 1" : "=r" (rt) );
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PAD_ORI
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PAD_ORI
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RESTORE_REGS(temp);
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RESTORE_REG_27(temp);
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}
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static void test_pld_off0_R1 (void) {
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SAVE_REGS(temp);
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SAVE_REG_27(temp);
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PAD_ORI
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__asm__ __volatile__ ("pld %0, +0(0), 1" : "=r" (rt) );
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PAD_ORI
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RESTORE_REGS(temp);
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RESTORE_REG_27(temp);
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}
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static void test_pld_off8_R1 (void) {
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SAVE_REGS(temp);
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SAVE_REG_27(temp);
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PAD_ORI
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__asm__ __volatile__ ("pld %0, +8(0), 1" : "=r" (rt) );
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PAD_ORI
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RESTORE_REGS(temp);
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RESTORE_REG_27(temp);
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}
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static void test_pld_off16_R1 (void) {
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SAVE_REGS(temp);
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SAVE_REG_27(temp);
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PAD_ORI
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__asm__ __volatile__ ("pld %0, +16(0), 1" : "=r" (rt) );
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PAD_ORI
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RESTORE_REGS(temp);
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RESTORE_REG_27(temp);
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}
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static void test_pld_off32_R1 (void) {
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SAVE_REGS(temp);
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SAVE_REG_27(temp);
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PAD_ORI
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__asm__ __volatile__ ("pld %0, +32(0), 1" : "=r" (rt) );
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PAD_ORI
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RESTORE_REGS(temp);
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RESTORE_REG_27(temp);
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}
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static void test_pld_off64_R1 (void) {
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SAVE_REGS(temp);
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SAVE_REG_27(temp);
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PAD_ORI
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__asm__ __volatile__ ("pld %0, +64(0), 1" : "=r" (rt) );
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PAD_ORI
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PAD_ORI
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RESTORE_REGS(temp);
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RESTORE_REG_27(temp);
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}
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static void test_pstb_off0_R1 (void) {
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__asm__ __volatile__ ("pstb %0, -0x1f400+0(0), 1" :: "r" (rs) );
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@ -298,35 +534,49 @@ static void test_paddi_98_R1 (void) {
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rt = 0xffff0098;
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}
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static void test_plq_off0_R1 (void) {
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SAVE_REGS(temp);
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PAD_ORI
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__asm__ __volatile__ ("plq 26, +0(0), 1" );
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__asm__ __volatile__ ("plq %0, +0(0), 1" : "=r" (rt) );
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PAD_ORI
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RESTORE_REGS(temp);
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}
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static void test_plq_off8_R1 (void) {
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SAVE_REGS(temp);
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PAD_ORI
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__asm__ __volatile__ ("plq 26, +8(0), 1" );
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__asm__ __volatile__ ("plq %0, +8(0), 1" : "=r" (rt) );
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PAD_ORI
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RESTORE_REGS(temp);
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}
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static void test_plq_off16_R1 (void) {
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SAVE_REGS(temp);
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PAD_ORI
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__asm__ __volatile__ ("plq 26, +16(0), 1" );
|
||||
__asm__ __volatile__ ("plq %0, +16(0), 1" : "=r" (rt) );
|
||||
PAD_ORI
|
||||
RESTORE_REGS(temp);
|
||||
}
|
||||
static void test_plq_off32_R1 (void) {
|
||||
SAVE_REGS(temp);
|
||||
PAD_ORI
|
||||
__asm__ __volatile__ ("plq 26, +32(0), 1" );
|
||||
__asm__ __volatile__ ("plq %0, +32(0), 1" : "=r" (rt) );
|
||||
PAD_ORI
|
||||
RESTORE_REGS(temp);
|
||||
}
|
||||
static void test_plq_off48_R1 (void) {
|
||||
SAVE_REGS(temp);
|
||||
PAD_ORI
|
||||
__asm__ __volatile__ ("plq 26, +48(0), 1" );
|
||||
__asm__ __volatile__ ("plq %0, +48(0), 1" : "=r" (rt) );
|
||||
PAD_ORI
|
||||
RESTORE_REGS(temp);
|
||||
}
|
||||
static void test_plq_off64_R1 (void) {
|
||||
SAVE_REGS(temp);
|
||||
SAVE_REG_RT(temp);
|
||||
PAD_ORI
|
||||
__asm__ __volatile__ ("plq 26, +64(0), 1" );
|
||||
__asm__ __volatile__ ("plq %0, +64(0), 1" : "=r" (rt) );
|
||||
PAD_ORI
|
||||
PAD_ORI
|
||||
RESTORE_REGS(temp);
|
||||
RESTORE_REG_RT(temp);
|
||||
}
|
||||
static void test_pstq_off0_R1 (void) {
|
||||
__asm__ __volatile__ ("pstq 24, -0x1f400+0(0), 1" );
|
||||
|
||||
@ -16,9 +16,9 @@ plbz off32_R1 => 1b
|
||||
|
||||
plbz off64_R1 => 1b
|
||||
|
||||
pld off0_R1 => e740000004100000
|
||||
pld off0_R1 => e74000000410001a
|
||||
|
||||
pld off8_R1 => 4e800020
|
||||
pld off8_R1 => 62d6001662b5001f
|
||||
|
||||
pld off16_R1 => 6318001862f7001f
|
||||
|
||||
@ -52,11 +52,11 @@ plq off8_R1 => 62d6001662b5001f 6318001862f7001f
|
||||
|
||||
plq off16_R1 => 6318001862f7001f 635a001a6339001b
|
||||
|
||||
plq off32_R1 => 639c001c637b001b 4e80003b
|
||||
plq off32_R1 => 639c001c637b001b eac90008eaa9001b
|
||||
|
||||
plq off48_R1 => 1a 62d6001662b5001f
|
||||
plq off48_R1 => eb090018eae9001a eb890038eb29003b
|
||||
|
||||
plq off64_R1 => 639c001c637b001b 4e80003b
|
||||
plq off64_R1 => 1111111111111111 eac90008eaa9001b
|
||||
|
||||
plwa off0_R1 => 4100000
|
||||
|
||||
@ -82,11 +82,11 @@ plxvp off0_R1 => 6318001862f70017 635a001a63390019 ea80000004100000 62d6001662b5
|
||||
|
||||
plxvp off8_R1 => 635a001a63390019 639c001c637b001b 62d6001662b50015 6318001862f70017
|
||||
|
||||
plxvp off16_R1 => 639c001c637b001b 000000004e800020 6318001862f70017 635a001a63390019
|
||||
plxvp off16_R1 => 639c001c637b001b eac90008eaa90000 6318001862f70017 635a001a63390019
|
||||
|
||||
plxvp off24_R1 => 000000004e800020 0000000000000000 635a001a63390019 639c001c637b001b
|
||||
plxvp off24_R1 => eac90008eaa90000 eb090018eae90010 635a001a63390019 639c001c637b001b
|
||||
|
||||
plxvp off32_R1 => 0000000000000000 62d6001662b50015 639c001c637b001b 000000004e800020
|
||||
plxvp off32_R1 => eb090018eae90010 eb890038eb290020 639c001c637b001b eac90008eaa90000
|
||||
|
||||
pstb off0_R1 102030405060708 => 08
|
||||
|
||||
|
||||
@ -48,6 +48,96 @@ unsigned long current_fpscr;
|
||||
struct test_list_t current_test;
|
||||
|
||||
#include "isa_3_1_helpers.h"
|
||||
#ifdef __powerpc64__
|
||||
typedef uint64_t HWord_t;
|
||||
|
||||
/* Save and restore all of the registers. Need to ensure the PAD_ORI does not change
|
||||
the other registers. This really shouldn't be needed but the optimization gets
|
||||
messed up when it inlines the test function. */
|
||||
#define SAVE_REGS(addr) \
|
||||
asm volatile( \
|
||||
" std 21, 0(%0) \n" \
|
||||
" std 22, 8(%0) \n" \
|
||||
" std 23, 16(%0) \n" \
|
||||
" std 24, 24(%0) \n" \
|
||||
" std 25, 32(%0) \n" \
|
||||
" std 26, 40(%0) \n" \
|
||||
" std 27, 48(%0) \n" \
|
||||
" std 29, 64(%0) \n" \
|
||||
" std 30, 72(%0) \n" \
|
||||
" std 31, 80(%0) \n" \
|
||||
::"b"(addr))
|
||||
|
||||
#define SAVE_REG_28(addr) \
|
||||
asm volatile( \
|
||||
" std 28, 56(%0) \n" \
|
||||
::"b"(addr))
|
||||
|
||||
#define RESTORE_REGS(addr) \
|
||||
asm volatile( \
|
||||
" ld 21, 0(%0) \n" \
|
||||
" ld 22, 8(%0) \n" \
|
||||
" ld 23, 16(%0) \n" \
|
||||
" ld 24, 24(%0) \n" \
|
||||
" ld 25, 32(%0) \n" \
|
||||
" ld 26, 40(%0) \n" \
|
||||
" ld 27, 48(%0) \n" \
|
||||
" ld 29, 64(%0) \n" \
|
||||
" ld 30, 72(%0) \n" \
|
||||
" ld 31, 80(%0) \n" \
|
||||
::"b"(addr))
|
||||
|
||||
#define RESTORE_REG_28(addr) \
|
||||
asm volatile( \
|
||||
" ld 28, 56(%0) \n" \
|
||||
::"b"(addr))
|
||||
|
||||
#else /* !__powerpc64__ */
|
||||
|
||||
typedef uint32_t HWord_t;
|
||||
#define SAVE_REGS(addr) \
|
||||
asm volatile( \
|
||||
" stw 21, 0(%0) \n" \
|
||||
" stw 22, 4(%0) \n" \
|
||||
" stw 23, 8(%0) \n" \
|
||||
" stw 24, 12(%0) \n" \
|
||||
" stw 25, 16(%0) \n" \
|
||||
" stw 26, 20(%0) \n" \
|
||||
" stw 27, 24(%0) \n" \
|
||||
" stw 29, 32(%0) \n" \
|
||||
" stw 30, 36(%0) \n" \
|
||||
" stw 31, 40(%0) \n" \
|
||||
::"b"(addr))
|
||||
|
||||
#define SAVE_REG_28(addr) \
|
||||
asm volatile( \
|
||||
" stw 28, 28(%0) \n" \
|
||||
::"b"(addr))
|
||||
|
||||
#define RESTORE_REGS(addr) \
|
||||
asm volatile( \
|
||||
" lwz 21, 0(%0) \n" \
|
||||
" lwz 22, 4(%0) \n" \
|
||||
" lwz 23, 8(%0) \n" \
|
||||
" lwz 24, 12(%0) \n" \
|
||||
" lwz 25, 16(%0) \n" \
|
||||
" lwz 26, 20(%0) \n" \
|
||||
" lwz 27, 24(%0) \n" \
|
||||
" lwz 29, 32(%0) \n" \
|
||||
" lwz 30, 36(%0) \n" \
|
||||
" lwz 31, 400(%0) \n" \
|
||||
::"b"(addr))
|
||||
|
||||
#define RESTORE_REG_28(addr) \
|
||||
asm volatile( \
|
||||
" lwz 28, 28(%0) \n" \
|
||||
::"b"(addr))
|
||||
#endif /* __powerpc64__ */
|
||||
|
||||
#define NUM_ENTRIES_SAVE_RESTORE 11
|
||||
|
||||
HWord_t temp[NUM_ENTRIES_SAVE_RESTORE];
|
||||
|
||||
static void test_pstxvp_off0_R1 (void) {
|
||||
__asm__ __volatile__ ("pstxvp 20, -0x1f400+0(0),1");
|
||||
}
|
||||
@ -61,54 +151,78 @@ static void test_pstxvp_off48_R1 (void) {
|
||||
__asm__ __volatile__ ("pstxvp 20, -0x1f400+48(0),1");
|
||||
}
|
||||
static void test_plfd_64_R1 (void) {
|
||||
SAVE_REGS(temp);
|
||||
__asm__ __volatile__ ("plfd 28, +64(0), 1");
|
||||
PAD_ORI
|
||||
PAD_ORI
|
||||
RESTORE_REGS(temp);
|
||||
}
|
||||
static void test_plfd_32_R1 (void) {
|
||||
SAVE_REGS(temp);
|
||||
__asm__ __volatile__ ("plfd 28, +32(0), 1");
|
||||
PAD_ORI
|
||||
RESTORE_REGS(temp);
|
||||
}
|
||||
static void test_plfd_16_R1 (void) {
|
||||
SAVE_REGS(temp);
|
||||
__asm__ __volatile__ ("plfd 28, +16(0), 1");
|
||||
PAD_ORI
|
||||
RESTORE_REGS(temp);
|
||||
}
|
||||
static void test_plfd_8_R1 (void) {
|
||||
SAVE_REGS(temp);
|
||||
__asm__ __volatile__ ("plfd 28, +8(0), 1");
|
||||
PAD_ORI
|
||||
RESTORE_REGS(temp);
|
||||
}
|
||||
static void test_plfd_4_R1 (void) {
|
||||
SAVE_REGS(temp);
|
||||
__asm__ __volatile__ ("plfd 28, +4(0), 1");
|
||||
PAD_ORI
|
||||
RESTORE_REGS(temp);
|
||||
}
|
||||
static void test_plfd_0_R1 (void) {
|
||||
SAVE_REGS(temp);
|
||||
__asm__ __volatile__ ("plfd 28, +0(0), 1");
|
||||
PAD_ORI
|
||||
RESTORE_REGS(temp);
|
||||
}
|
||||
static void test_plfs_64_R1 (void) {
|
||||
SAVE_REGS(temp);
|
||||
__asm__ __volatile__ ("plfs 28, +64(0), 1");
|
||||
PAD_ORI
|
||||
PAD_ORI
|
||||
RESTORE_REGS(temp);
|
||||
}
|
||||
static void test_plfs_32_R1 (void) {
|
||||
SAVE_REGS(temp);
|
||||
__asm__ __volatile__ ("plfs 28, +32(0), 1");
|
||||
PAD_ORI
|
||||
RESTORE_REGS(temp);
|
||||
}
|
||||
static void test_plfs_16_R1 (void) {
|
||||
SAVE_REGS(temp);
|
||||
__asm__ __volatile__ ("plfs 28, +16(0), 1");
|
||||
PAD_ORI
|
||||
RESTORE_REGS(temp);
|
||||
}
|
||||
static void test_plfs_8_R1 (void) {
|
||||
SAVE_REGS(temp);
|
||||
__asm__ __volatile__ ("plfs 28, +8(0), 1");
|
||||
PAD_ORI
|
||||
RESTORE_REGS(temp);
|
||||
}
|
||||
static void test_plfs_4_R1 (void) {
|
||||
SAVE_REGS(temp);
|
||||
__asm__ __volatile__ ("plfs 28, +4(0), 1");
|
||||
PAD_ORI
|
||||
RESTORE_REGS(temp);
|
||||
}
|
||||
static void test_plfs_0_R1 (void) {
|
||||
SAVE_REGS(temp);
|
||||
__asm__ __volatile__ ("plfs 28, +0(0), 1");
|
||||
PAD_ORI
|
||||
RESTORE_REGS(temp);
|
||||
}
|
||||
static void test_pstfd_32_R1 (void) {
|
||||
__asm__ __volatile__ ("pstfd 26, -0x1f400+32(0), 1");
|
||||
@ -141,54 +255,102 @@ static void test_pstfs_0_R1 (void) {
|
||||
__asm__ __volatile__ ("pstfs 26, -0x1f400+0(0), 1");
|
||||
}
|
||||
static void test_plxsd_64_R1 (void) {
|
||||
SAVE_REGS(temp);
|
||||
SAVE_REG_28(temp);
|
||||
__asm__ __volatile__ ("plxsd %0, +64(0), 1" : "=v" (vrt) );
|
||||
PAD_ORI
|
||||
PAD_ORI
|
||||
RESTORE_REGS(temp);
|
||||
RESTORE_REG_28(temp);
|
||||
}
|
||||
static void test_plxsd_32_R1 (void) {
|
||||
SAVE_REGS(temp);
|
||||
SAVE_REG_28(temp);
|
||||
__asm__ __volatile__ (".align 2 ; plxsd %0, +32(0), 1" : "=v" (vrt) );
|
||||
PAD_ORI
|
||||
RESTORE_REGS(temp);
|
||||
RESTORE_REG_28(temp);
|
||||
}
|
||||
static void test_plxsd_16_R1 (void) {
|
||||
SAVE_REGS(temp);
|
||||
SAVE_REG_28(temp);
|
||||
__asm__ __volatile__ ("plxsd %0, +16(0), 1; pnop;pnop;pnop; " : "=v" (vrt) );
|
||||
PAD_ORI
|
||||
RESTORE_REGS(temp);
|
||||
RESTORE_REG_28(temp);
|
||||
}
|
||||
static void test_plxsd_8_R1 (void) {
|
||||
SAVE_REGS(temp);
|
||||
SAVE_REG_28(temp);
|
||||
__asm__ __volatile__ ("plxsd %0, +8(0), 1; pnop;pnop;pnop; " : "=v" (vrt) );
|
||||
PAD_ORI
|
||||
RESTORE_REGS(temp);
|
||||
RESTORE_REG_28(temp);
|
||||
}
|
||||
static void test_plxsd_4_R1 (void) {
|
||||
SAVE_REGS(temp);
|
||||
SAVE_REG_28(temp);
|
||||
__asm__ __volatile__ ("plxsd %0, +4(0), 1; pnop;pnop;pnop; " : "=v" (vrt) );
|
||||
PAD_ORI
|
||||
RESTORE_REGS(temp);
|
||||
RESTORE_REG_28(temp);
|
||||
}
|
||||
static void test_plxsd_0_R1 (void) {
|
||||
SAVE_REGS(temp);
|
||||
SAVE_REG_28(temp);
|
||||
__asm__ __volatile__ ("plxsd %0, +0(0), 1; pnop;pnop;pnop; " : "=v" (vrt) );
|
||||
PAD_ORI
|
||||
RESTORE_REGS(temp);
|
||||
RESTORE_REG_28(temp);
|
||||
}
|
||||
static void test_plxssp_64_R1 (void) {
|
||||
SAVE_REGS(temp);
|
||||
SAVE_REG_28(temp);
|
||||
__asm__ __volatile__ ("plxssp %0, +64(0), 1; pnop;pnop;pnop; " : "=v" (vrt) );
|
||||
PAD_ORI
|
||||
PAD_ORI
|
||||
RESTORE_REGS(temp);
|
||||
RESTORE_REG_28(temp);
|
||||
}
|
||||
static void test_plxssp_32_R1 (void) {
|
||||
SAVE_REGS(temp);
|
||||
SAVE_REG_28(temp);
|
||||
__asm__ __volatile__ ("plxssp %0, +32(0), 1; pnop; " : "=v" (vrt) );
|
||||
PAD_ORI
|
||||
RESTORE_REGS(temp);
|
||||
RESTORE_REG_28(temp);
|
||||
}
|
||||
static void test_plxssp_16_R1 (void) {
|
||||
SAVE_REGS(temp);
|
||||
SAVE_REG_28(temp);
|
||||
__asm__ __volatile__ ("plxssp %0, +16(0), 1; pnop;pnop;pnop; " : "=v" (vrt) );
|
||||
PAD_ORI
|
||||
RESTORE_REGS(temp);
|
||||
RESTORE_REG_28(temp);
|
||||
}
|
||||
static void test_plxssp_8_R1 (void) {
|
||||
SAVE_REGS(temp);
|
||||
SAVE_REG_28(temp);
|
||||
__asm__ __volatile__ ("plxssp %0, +8(0), 1; pnop;pnop;pnop; " : "=v" (vrt) );
|
||||
PAD_ORI
|
||||
RESTORE_REGS(temp);
|
||||
RESTORE_REG_28(temp);
|
||||
}
|
||||
static void test_plxssp_4_R1 (void) {
|
||||
SAVE_REGS(temp);
|
||||
SAVE_REG_28(temp);
|
||||
__asm__ __volatile__ ("plxssp %0, +4(0), 1; pnop;pnop;pnop; " : "=v" (vrt) );
|
||||
PAD_ORI
|
||||
RESTORE_REGS(temp);
|
||||
RESTORE_REG_28(temp);
|
||||
}
|
||||
static void test_plxssp_0_R1 (void) {
|
||||
SAVE_REGS(temp);
|
||||
SAVE_REG_28(temp);
|
||||
__asm__ __volatile__ ("plxssp %0, +0(0), 1; pnop;pnop;pnop; " : "=v" (vrt) );
|
||||
PAD_ORI
|
||||
RESTORE_REGS(temp);
|
||||
RESTORE_REG_28(temp);
|
||||
}
|
||||
/* Follow the short-range plxv instructions with nop in order to
|
||||
pad out subsequent instructions. When written there are found
|
||||
@ -196,20 +358,36 @@ static void test_plxssp_0_R1 (void) {
|
||||
into the target variable. (pla,pstxv...).
|
||||
*/
|
||||
static void test_plxv_16_R1 (void) {
|
||||
SAVE_REGS(temp);
|
||||
SAVE_REG_28(temp);
|
||||
__asm__ __volatile__ ("plxv %x0, +16(0), 1; pnop;pnop;pnop;" : "=wa" (vec_xt) );
|
||||
PAD_ORI
|
||||
RESTORE_REGS(temp);
|
||||
RESTORE_REG_28(temp);
|
||||
}
|
||||
static void test_plxv_8_R1 (void) {
|
||||
SAVE_REGS(temp);
|
||||
SAVE_REG_28(temp);
|
||||
__asm__ __volatile__ ("plxv %x0, +8(0), 1; pnop;pnop;pnop;" : "=wa" (vec_xt) );
|
||||
PAD_ORI
|
||||
RESTORE_REGS(temp);
|
||||
RESTORE_REG_28(temp);
|
||||
}
|
||||
static void test_plxv_4_R1 (void) {
|
||||
SAVE_REGS(temp);
|
||||
SAVE_REG_28(temp);
|
||||
__asm__ __volatile__ ("plxv %x0, +4(0), 1; pnop;pnop;pnop;" : "=wa" (vec_xt) );
|
||||
PAD_ORI
|
||||
RESTORE_REGS(temp);
|
||||
RESTORE_REG_28(temp);
|
||||
}
|
||||
static void test_plxv_0_R1 (void) {
|
||||
SAVE_REGS(temp);
|
||||
SAVE_REG_28(temp);
|
||||
__asm__ __volatile__ ("plxv %x0, +0(0), 1; pnop;pnop;pnop; " : "=wa" (vec_xt) );
|
||||
PAD_ORI
|
||||
RESTORE_REGS(temp);
|
||||
RESTORE_REG_28(temp);
|
||||
}
|
||||
static void test_pstxsd_64_R1 (void) {
|
||||
__asm__ __volatile__ (".align 2 ; pstxsd 22, -0x1f400+64(0), 1" );
|
||||
|
||||
@ -26,9 +26,9 @@ plxsd 0_R1 => a800000004100000,0000000000000000 -5.07588375e-116 +Zer
|
||||
|
||||
plxsd 4_R1 => 7000000a8000004,0000000000000000 5.77662562e-275 +Zero
|
||||
|
||||
plxsd 8_R1 => 700000060000000,0000000000000000 5.77662407e-275 +Zero
|
||||
plxsd 8_R1 => 7000000,0000000000000000 +Den +Zero
|
||||
|
||||
plxsd 16_R1 => 7000000,0000000000000000 +Den +Zero
|
||||
plxsd 16_R1 => 700000060000000,0000000000000000 5.77662407e-275 +Zero
|
||||
|
||||
plxsd 32_R1 => 6339001963180018,0000000000000000 9.43505226e+169 +Zero
|
||||
|
||||
@ -38,21 +38,21 @@ plxssp 0_R1 => 3882000000000000,0000000000000000 6.19888e-05 +Zero
|
||||
|
||||
plxssp 4_R1 => bd80000080000000,0000000000000000 -6.25000e-02 -Zero +Zero +Zero
|
||||
|
||||
plxssp 8_R1 => 38e0000000000000,0000000000000000 1.06812e-04 +Zero +Zero +Zero
|
||||
plxssp 8_R1 => 4400000000000000,0000000000000000 5.12000e+02 +Zero +Zero +Zero
|
||||
|
||||
plxssp 16_R1 => 38e0000000000000,0000000000000000 1.06812e-04 +Zero +Zero +Zero
|
||||
|
||||
plxssp 32_R1 => 445ac002c0000000,0000000000000000 8.75000e+02 -2.00000e+00 +Zero +Zero
|
||||
|
||||
plxssp 64_R1 => 446b400340000000,0000000000000000 9.41000e+02 2.00000e+00 +Zero +Zero
|
||||
plxssp 64_R1 => 4467200320000000,0000000000000000 9.24500e+02 1.08420e-19 +Zero +Zero
|
||||
|
||||
plxv 0_R1 => c800000004100000 7000000
|
||||
plxv 0_R1 => c800000004100000 700000060000000
|
||||
|
||||
plxv 4_R1 => 7000000c8000004 700000000000000
|
||||
plxv 4_R1 => 60000000c8000004 7000000
|
||||
|
||||
plxv 8_R1 => 7000000 7000000
|
||||
plxv 8_R1 => 700000060000000 700000000000000
|
||||
|
||||
plxv 16_R1 => 7000000 7000000
|
||||
plxv 16_R1 => 700000000000000 700000000000000
|
||||
|
||||
pstfd 0_R1 43dfe000003fe000 43eff000000ff000 => e000003fe00043df
|
||||
pstfd 0_R1 43eff000000ff000 43efefffffcff000 => f000000ff00043ef
|
||||
|
||||
Loading…
x
Reference in New Issue
Block a user