mirror of
https://github.com/Zenithsiz/ftmemsim-valgrind.git
synced 2026-02-03 10:05:29 +00:00
Add tests to verify behaviour of atomic instruction handling.
git-svn-id: svn://svn.valgrind.org/valgrind/trunk@10410
This commit is contained in:
Julian Seward
parent
657d0e65eb
commit
205f7fa457
@ -36,6 +36,8 @@ noinst_HEADERS = leak.h
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EXTRA_DIST = \
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addressable.stderr.exp addressable.stdout.exp addressable.vgtest \
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atomic_incs.stderr.exp atomic_incs.vgtest \
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atomic_incs.stdout.exp-32bit atomic_incs.stdout.exp-64bit \
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badaddrvalue.stderr.exp \
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badaddrvalue.stdout.exp badaddrvalue.vgtest \
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badfree-2trace.stderr.exp badfree-2trace.vgtest \
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@ -183,6 +185,7 @@ EXTRA_DIST = \
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check_PROGRAMS = \
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addressable \
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atomic_incs \
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badaddrvalue badfree badjump badjump2 \
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badloop badpoll badrw brk2 buflen_check \
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clientperm custom_alloc \
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192
memcheck/tests/atomic_incs.c
Normal file
192
memcheck/tests/atomic_incs.c
Normal file
@ -0,0 +1,192 @@
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/* This is an example of a program which does atomic memory operations
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between two processes which share a page. Valgrind 3.4.1 and
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earlier produce incorrect answers because it does not preserve
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atomicity of the relevant instructions in the generated code; but
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the post-DCAS-merge versions of Valgrind do behave correctly. */
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#include <stdlib.h>
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#include <stdio.h>
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#include <assert.h>
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#include <unistd.h>
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#include <sys/wait.h>
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#include <sys/mman.h>
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#define NNN 3456987
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__attribute__((noinline)) void atomic_add_8bit ( char* p, int n )
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{
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unsigned long block[2];
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block[0] = (unsigned long)p;
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block[1] = n;
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#if defined(VGA_x86)
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__asm__ __volatile__(
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"movl 0(%%esi),%%eax" "\n\t"
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"movl 4(%%esi),%%ebx" "\n\t"
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"lock; addb %%bl,(%%eax)" "\n"
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: : "S"(&block[0])/* S means "esi only" */ : "memory","cc","eax","ebx"
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);
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#elif defined(VGA_amd64)
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__asm__ __volatile__(
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"movq 0(%%rsi),%%rax" "\n\t"
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"movq 8(%%rsi),%%rbx" "\n\t"
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"lock; addb %%bl,(%%rax)" "\n"
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: : "S"(&block[0])/* S means "rsi only" */ : "memory","cc","rax","rbx"
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);
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#else
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# error "Unsupported arch"
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#endif
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}
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__attribute__((noinline)) void atomic_add_16bit ( short* p, int n )
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{
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unsigned long block[2];
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block[0] = (unsigned long)p;
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block[1] = n;
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#if defined(VGA_x86)
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__asm__ __volatile__(
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"movl 0(%%esi),%%eax" "\n\t"
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"movl 4(%%esi),%%ebx" "\n\t"
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"lock; addw %%bx,(%%eax)" "\n"
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: : "S"(&block[0])/* S means "esi only" */ : "memory","cc","eax","ebx"
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);
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#elif defined(VGA_amd64)
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__asm__ __volatile__(
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"movq 0(%%rsi),%%rax" "\n\t"
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"movq 8(%%rsi),%%rbx" "\n\t"
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"lock; addw %%bx,(%%rax)" "\n"
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: : "S"(&block[0])/* S means "rsi only" */ : "memory","cc","rax","rbx"
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);
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#else
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# error "Unsupported arch"
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#endif
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}
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__attribute__((noinline)) void atomic_add_32bit ( int* p, int n )
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{
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unsigned long block[2];
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block[0] = (unsigned long)p;
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block[1] = n;
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#if defined(VGA_x86)
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__asm__ __volatile__(
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"movl 0(%%esi),%%eax" "\n\t"
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"movl 4(%%esi),%%ebx" "\n\t"
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"lock; addl %%ebx,(%%eax)" "\n"
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: : "S"(&block[0])/* S means "esi only" */ : "memory","cc","eax","ebx"
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);
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#elif defined(VGA_amd64)
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__asm__ __volatile__(
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"movq 0(%%rsi),%%rax" "\n\t"
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"movq 8(%%rsi),%%rbx" "\n\t"
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"lock; addl %%ebx,(%%rax)" "\n"
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: : "S"(&block[0])/* S means "rsi only" */ : "memory","cc","rax","rbx"
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);
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#else
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# error "Unsupported arch"
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#endif
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}
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__attribute__((noinline)) void atomic_add_64bit ( long long int* p, int n )
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{
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// this is a bit subtle. It relies on the fact that, on a 64-bit platform,
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// sizeof(unsigned long long int) == sizeof(unsigned long) == sizeof(void*)
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unsigned long long int block[2];
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block[0] = (unsigned long long int)(unsigned long)p;
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block[1] = n;
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#if defined(VGA_x86)
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/* do nothing; is not supported */
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#elif defined(VGA_amd64)
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__asm__ __volatile__(
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"movq 0(%%rsi),%%rax" "\n\t"
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"movq 8(%%rsi),%%rbx" "\n\t"
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"lock; addq %%rbx,(%%rax)" "\n"
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: : "S"(&block[0])/* S means "rsi only" */ : "memory","cc","rax","rbx"
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);
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#else
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# error "Unsupported arch"
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#endif
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}
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int main ( int argc, char** argv )
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{
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int i, status;
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char* page;
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char* p8;
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short* p16;
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int* p32;
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long long int* p64;
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pid_t child, p2;
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printf("parent, pre-fork\n");
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page = mmap( 0, sysconf(_SC_PAGESIZE),
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PROT_READ|PROT_WRITE,
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MAP_ANONYMOUS|MAP_SHARED, -1, 0 );
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if (page == MAP_FAILED) {
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perror("mmap failed");
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exit(1);
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}
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p8 = (char*)(page+0);
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p16 = (short*)(page+256);
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p32 = (int*)(page+512);
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p64 = (long long int*)(page+768);
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*p8 = 0;
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*p16 = 0;
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*p32 = 0;
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*p64 = 0;
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child = fork();
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if (child == -1) {
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perror("fork() failed\n");
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return 1;
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}
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if (child == 0) {
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/* --- CHILD --- */
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printf("child\n");
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for (i = 0; i < NNN; i++) {
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atomic_add_8bit(p8, 1);
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atomic_add_16bit(p16, 1);
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atomic_add_32bit(p32, 1);
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atomic_add_64bit(p64, 98765 ); /* ensure we hit the upper 32 bits */
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}
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return 1;
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/* NOTREACHED */
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}
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/* --- PARENT --- */
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printf("parent\n");
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for (i = 0; i < NNN; i++) {
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atomic_add_8bit(p8, 1);
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atomic_add_16bit(p16, 1);
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atomic_add_32bit(p32, 1);
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atomic_add_64bit(p64, 98765 ); /* ensure we hit the upper 32 bits */
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}
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p2 = waitpid(child, &status, 0);
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assert(p2 == child);
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/* assert that child finished normally */
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assert(WIFEXITED(status));
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printf("FINAL VALUES: 8 bit %d, 16 bit %d, 32 bit %d, 64 bit %lld\n",
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(int)(*p8), (int)(*p16), *p32, *p64 );
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if (-74 == (int)(*p8)
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&& 32694 == (int)(*p16)
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&& 6913974 == *p32
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&& (0LL == *p64 || 682858642110 == *p64)) {
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printf("PASS\n");
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} else {
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printf("FAIL -- see source code for expected values\n");
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}
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printf("parent exits\n");
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return 0;
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}
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0
memcheck/tests/atomic_incs.stderr.exp
Normal file
0
memcheck/tests/atomic_incs.stderr.exp
Normal file
0
memcheck/tests/atomic_incs.stdout.exp-32bit
Normal file
0
memcheck/tests/atomic_incs.stdout.exp-32bit
Normal file
7
memcheck/tests/atomic_incs.stdout.exp-64bit
Normal file
7
memcheck/tests/atomic_incs.stdout.exp-64bit
Normal file
@ -0,0 +1,7 @@
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parent, pre-fork
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child
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parent, pre-fork
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parent
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FINAL VALUES: 8 bit -74, 16 bit 32694, 32 bit 6913974, 64 bit 682858642110
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PASS
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parent exits
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2
memcheck/tests/atomic_incs.vgtest
Normal file
2
memcheck/tests/atomic_incs.vgtest
Normal file
@ -0,0 +1,2 @@
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prog: atomic_incs
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vgopts: -q --track-origins=yes
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@ -17,6 +17,7 @@ endif
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# to avoid packaging screwups if 'make dist' is run on a machine
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# which failed the BUILD_SSE3_TESTS test in configure.in.
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EXTRA_DIST = \
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amd64locked.vgtest amd64locked.stdout.exp amd64locked.stderr.exp \
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bug127521-64.vgtest bug127521-64.stdout.exp bug127521-64.stderr.exp \
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bug132813-amd64.vgtest bug132813-amd64.stdout.exp \
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bug132813-amd64.stderr.exp \
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@ -50,6 +51,7 @@ EXTRA_DIST = \
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slahf-amd64.vgtest
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check_PROGRAMS = \
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amd64locked \
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bug127521-64 bug132813-amd64 bug132918 \
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clc \
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$(INSN_TESTS) \
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@ -80,6 +82,7 @@ AM_CXXFLAGS += @FLAG_M64@
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AM_CCASFLAGS += @FLAG_M64@
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# generic C ones
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amd64locked_CFLAGS = $(AM_CFLAGS) -O
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bug132918_LDADD = -lm
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insn_basic_SOURCES = insn_basic.def
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insn_basic_LDADD = -lm
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1062
none/tests/amd64/amd64locked.c
Normal file
1062
none/tests/amd64/amd64locked.c
Normal file
File diff suppressed because it is too large
Load Diff
2
none/tests/amd64/amd64locked.stderr.exp
Normal file
2
none/tests/amd64/amd64locked.stderr.exp
Normal file
@ -0,0 +1,2 @@
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1
none/tests/amd64/amd64locked.stdout.exp
Normal file
1
none/tests/amd64/amd64locked.stdout.exp
Normal file
@ -0,0 +1 @@
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amd64locked: PASS: CRCs actual 0x1F677629 expected 0x1F677629
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1
none/tests/amd64/amd64locked.vgtest
Normal file
1
none/tests/amd64/amd64locked.vgtest
Normal file
@ -0,0 +1 @@
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prog: amd64locked
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@ -52,6 +52,7 @@ EXTRA_DIST = \
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smc1.stderr.exp smc1.stdout.exp smc1.vgtest \
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ssse3_misaligned.stderr.exp ssse3_misaligned.stdout.exp \
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ssse3_misaligned.vgtest ssse3_misaligned.c \
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x86locked.vgtest x86locked.stdout.exp x86locked.stderr.exp \
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yield.stderr.exp yield.stdout.exp yield.disabled
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check_PROGRAMS = \
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@ -82,6 +83,7 @@ check_PROGRAMS = \
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pushpopseg \
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sbbmisc \
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smc1 \
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x86locked \
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yield
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if BUILD_SSSE3_TESTS
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check_PROGRAMS += ssse3_misaligned
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@ -123,6 +125,7 @@ insn_sse3_SOURCES = insn_sse3.def
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insn_sse3_LDADD = -lm
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insn_ssse3_SOURCES = insn_ssse3.def
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insn_ssse3_LDADD = -lm
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x86locked_CFLAGS = $(AM_CFLAGS) -O
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yield_LDADD = -lpthread
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.def.c: $(srcdir)/gen_insn_test.pl
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864
none/tests/x86/x86locked.c
Normal file
864
none/tests/x86/x86locked.c
Normal file
@ -0,0 +1,864 @@
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#include <stdio.h>
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#include <stdlib.h>
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#include <assert.h>
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#define VERBOSE 0
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typedef unsigned int UInt;
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typedef unsigned char UChar;
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typedef unsigned long long int ULong;
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typedef signed long long int Long;
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typedef signed int Int;
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typedef unsigned short UShort;
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typedef unsigned long UWord;
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typedef char HChar;
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/////////////////////////////////////////////////////////////////
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// BEGIN crc32 stuff //
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/////////////////////////////////////////////////////////////////
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static const UInt crc32Table[256] = {
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/*-- Ugly, innit? --*/
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0x00000000L, 0x04c11db7L, 0x09823b6eL, 0x0d4326d9L,
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0x130476dcL, 0x17c56b6bL, 0x1a864db2L, 0x1e475005L,
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0x2608edb8L, 0x22c9f00fL, 0x2f8ad6d6L, 0x2b4bcb61L,
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0x350c9b64L, 0x31cd86d3L, 0x3c8ea00aL, 0x384fbdbdL,
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0x4c11db70L, 0x48d0c6c7L, 0x4593e01eL, 0x4152fda9L,
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0x5f15adacL, 0x5bd4b01bL, 0x569796c2L, 0x52568b75L,
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0x6a1936c8L, 0x6ed82b7fL, 0x639b0da6L, 0x675a1011L,
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0x791d4014L, 0x7ddc5da3L, 0x709f7b7aL, 0x745e66cdL,
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0x9823b6e0L, 0x9ce2ab57L, 0x91a18d8eL, 0x95609039L,
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0x8b27c03cL, 0x8fe6dd8bL, 0x82a5fb52L, 0x8664e6e5L,
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0xbe2b5b58L, 0xbaea46efL, 0xb7a96036L, 0xb3687d81L,
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0xad2f2d84L, 0xa9ee3033L, 0xa4ad16eaL, 0xa06c0b5dL,
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0xd4326d90L, 0xd0f37027L, 0xddb056feL, 0xd9714b49L,
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0xc7361b4cL, 0xc3f706fbL, 0xceb42022L, 0xca753d95L,
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0xf23a8028L, 0xf6fb9d9fL, 0xfbb8bb46L, 0xff79a6f1L,
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0xe13ef6f4L, 0xe5ffeb43L, 0xe8bccd9aL, 0xec7dd02dL,
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0x34867077L, 0x30476dc0L, 0x3d044b19L, 0x39c556aeL,
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0x278206abL, 0x23431b1cL, 0x2e003dc5L, 0x2ac12072L,
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0x128e9dcfL, 0x164f8078L, 0x1b0ca6a1L, 0x1fcdbb16L,
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0x018aeb13L, 0x054bf6a4L, 0x0808d07dL, 0x0cc9cdcaL,
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0x7897ab07L, 0x7c56b6b0L, 0x71159069L, 0x75d48ddeL,
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0x6b93dddbL, 0x6f52c06cL, 0x6211e6b5L, 0x66d0fb02L,
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0x5e9f46bfL, 0x5a5e5b08L, 0x571d7dd1L, 0x53dc6066L,
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0x4d9b3063L, 0x495a2dd4L, 0x44190b0dL, 0x40d816baL,
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0xaca5c697L, 0xa864db20L, 0xa527fdf9L, 0xa1e6e04eL,
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0xbfa1b04bL, 0xbb60adfcL, 0xb6238b25L, 0xb2e29692L,
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0x8aad2b2fL, 0x8e6c3698L, 0x832f1041L, 0x87ee0df6L,
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0x99a95df3L, 0x9d684044L, 0x902b669dL, 0x94ea7b2aL,
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0xe0b41de7L, 0xe4750050L, 0xe9362689L, 0xedf73b3eL,
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0xf3b06b3bL, 0xf771768cL, 0xfa325055L, 0xfef34de2L,
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0xc6bcf05fL, 0xc27dede8L, 0xcf3ecb31L, 0xcbffd686L,
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0xd5b88683L, 0xd1799b34L, 0xdc3abdedL, 0xd8fba05aL,
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0x690ce0eeL, 0x6dcdfd59L, 0x608edb80L, 0x644fc637L,
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0x7a089632L, 0x7ec98b85L, 0x738aad5cL, 0x774bb0ebL,
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0x4f040d56L, 0x4bc510e1L, 0x46863638L, 0x42472b8fL,
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0x5c007b8aL, 0x58c1663dL, 0x558240e4L, 0x51435d53L,
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0x251d3b9eL, 0x21dc2629L, 0x2c9f00f0L, 0x285e1d47L,
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0x36194d42L, 0x32d850f5L, 0x3f9b762cL, 0x3b5a6b9bL,
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0x0315d626L, 0x07d4cb91L, 0x0a97ed48L, 0x0e56f0ffL,
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0x1011a0faL, 0x14d0bd4dL, 0x19939b94L, 0x1d528623L,
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0xf12f560eL, 0xf5ee4bb9L, 0xf8ad6d60L, 0xfc6c70d7L,
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0xe22b20d2L, 0xe6ea3d65L, 0xeba91bbcL, 0xef68060bL,
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0xd727bbb6L, 0xd3e6a601L, 0xdea580d8L, 0xda649d6fL,
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0xc423cd6aL, 0xc0e2d0ddL, 0xcda1f604L, 0xc960ebb3L,
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0xbd3e8d7eL, 0xb9ff90c9L, 0xb4bcb610L, 0xb07daba7L,
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0xae3afba2L, 0xaafbe615L, 0xa7b8c0ccL, 0xa379dd7bL,
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0x9b3660c6L, 0x9ff77d71L, 0x92b45ba8L, 0x9675461fL,
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0x8832161aL, 0x8cf30badL, 0x81b02d74L, 0x857130c3L,
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0x5d8a9099L, 0x594b8d2eL, 0x5408abf7L, 0x50c9b640L,
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0x4e8ee645L, 0x4a4ffbf2L, 0x470cdd2bL, 0x43cdc09cL,
|
||||
0x7b827d21L, 0x7f436096L, 0x7200464fL, 0x76c15bf8L,
|
||||
0x68860bfdL, 0x6c47164aL, 0x61043093L, 0x65c52d24L,
|
||||
0x119b4be9L, 0x155a565eL, 0x18197087L, 0x1cd86d30L,
|
||||
0x029f3d35L, 0x065e2082L, 0x0b1d065bL, 0x0fdc1becL,
|
||||
0x3793a651L, 0x3352bbe6L, 0x3e119d3fL, 0x3ad08088L,
|
||||
0x2497d08dL, 0x2056cd3aL, 0x2d15ebe3L, 0x29d4f654L,
|
||||
0xc5a92679L, 0xc1683bceL, 0xcc2b1d17L, 0xc8ea00a0L,
|
||||
0xd6ad50a5L, 0xd26c4d12L, 0xdf2f6bcbL, 0xdbee767cL,
|
||||
0xe3a1cbc1L, 0xe760d676L, 0xea23f0afL, 0xeee2ed18L,
|
||||
0xf0a5bd1dL, 0xf464a0aaL, 0xf9278673L, 0xfde69bc4L,
|
||||
0x89b8fd09L, 0x8d79e0beL, 0x803ac667L, 0x84fbdbd0L,
|
||||
0x9abc8bd5L, 0x9e7d9662L, 0x933eb0bbL, 0x97ffad0cL,
|
||||
0xafb010b1L, 0xab710d06L, 0xa6322bdfL, 0xa2f33668L,
|
||||
0xbcb4666dL, 0xb8757bdaL, 0xb5365d03L, 0xb1f740b4L
|
||||
};
|
||||
|
||||
#define UPDATE_CRC(crcVar,cha) \
|
||||
{ \
|
||||
crcVar = (crcVar << 8) ^ \
|
||||
crc32Table[(crcVar >> 24) ^ \
|
||||
((UChar)cha)]; \
|
||||
}
|
||||
|
||||
static UInt crcBytes ( UChar* bytes, UWord nBytes, UInt crcIn )
|
||||
{
|
||||
UInt crc = crcIn;
|
||||
while (nBytes >= 4) {
|
||||
UPDATE_CRC(crc, bytes[0]);
|
||||
UPDATE_CRC(crc, bytes[1]);
|
||||
UPDATE_CRC(crc, bytes[2]);
|
||||
UPDATE_CRC(crc, bytes[3]);
|
||||
bytes += 4;
|
||||
nBytes -= 4;
|
||||
}
|
||||
while (nBytes >= 1) {
|
||||
UPDATE_CRC(crc, bytes[0]);
|
||||
bytes += 1;
|
||||
nBytes -= 1;
|
||||
}
|
||||
return crc;
|
||||
}
|
||||
|
||||
static UInt crcFinalise ( UInt crc ) {
|
||||
return ~crc;
|
||||
}
|
||||
|
||||
////////
|
||||
|
||||
static UInt theCRC = 0xFFFFFFFF;
|
||||
|
||||
static HChar outBuf[1024];
|
||||
// take output that's in outBuf, length as specified, and
|
||||
// update the running crc.
|
||||
static void send ( int nbytes )
|
||||
{
|
||||
assert( ((unsigned int)nbytes) < sizeof(outBuf)-1);
|
||||
assert(outBuf[nbytes] == 0);
|
||||
theCRC = crcBytes( (UChar*)&outBuf[0], nbytes, theCRC );
|
||||
if (VERBOSE) printf("SEND %08x %s", theCRC, outBuf);
|
||||
}
|
||||
|
||||
|
||||
/////////////////////////////////////////////////////////////////
|
||||
// END crc32 stuff //
|
||||
/////////////////////////////////////////////////////////////////
|
||||
|
||||
#if 0
|
||||
|
||||
// full version
|
||||
#define NVALS 57
|
||||
|
||||
static unsigned int val[NVALS]
|
||||
= { 0x00, 0x01, 0x02, 0x03,
|
||||
0x3F, 0x40, 0x41,
|
||||
0x7E, 0x7F, 0x80, 0x81, 0x82,
|
||||
0xBF, 0xC0, 0xC1,
|
||||
0xFC, 0xFD, 0xFE, 0xFF,
|
||||
|
||||
0xFF00, 0xFF01, 0xFF02, 0xFF03,
|
||||
0xFF3F, 0xFF40, 0xFF41,
|
||||
0xFF7E, 0xFF7F, 0xFF80, 0xFF81, 0xFF82,
|
||||
0xFFBF, 0xFFC0, 0xFFC1,
|
||||
0xFFFC, 0xFFFD, 0xFFFE, 0xFFFF,
|
||||
|
||||
0xFFFFFF00, 0xFFFFFF01, 0xFFFFFF02, 0xFFFFFF03,
|
||||
0xFFFFFF3F, 0xFFFFFF40, 0xFFFFFF41,
|
||||
0xFFFFFF7E, 0xFFFFFF7F, 0xFFFFFF80, 0xFFFFFF81, 0xFFFFFF82,
|
||||
0xFFFFFFBF, 0xFFFFFFC0, 0xFFFFFFC1,
|
||||
0xFFFFFFFC, 0xFFFFFFFD, 0xFFFFFFFE, 0xFFFFFFFF
|
||||
};
|
||||
|
||||
#else
|
||||
|
||||
// shortened version, for use as valgrind regtest
|
||||
#define NVALS 27
|
||||
|
||||
static unsigned int val[NVALS]
|
||||
= { 0x00, 0x01,
|
||||
0x3F, 0x40,
|
||||
0x7F, 0x80,
|
||||
0xBF, 0xC0,
|
||||
0xFF,
|
||||
|
||||
0xFF00, 0xFF01,
|
||||
0xFF3F, 0xFF40,
|
||||
0xFF7F, 0xFF80,
|
||||
0xFFBF, 0xFFC0,
|
||||
0xFFFF,
|
||||
|
||||
0xFFFFFF00, 0xFFFFFF01,
|
||||
0xFFFFFF3F, 0xFFFFFF40,
|
||||
0xFFFFFF7F, 0xFFFFFF80,
|
||||
0xFFFFFFBF, 0xFFFFFFC0,
|
||||
0xFFFFFFFF
|
||||
};
|
||||
|
||||
#endif
|
||||
|
||||
/////////////////////////////////////
|
||||
|
||||
#define CC_C 0x0001
|
||||
#define CC_P 0x0004
|
||||
#define CC_A 0x0010
|
||||
#define CC_Z 0x0040
|
||||
#define CC_S 0x0080
|
||||
#define CC_O 0x0800
|
||||
|
||||
#define CC_MASK (CC_C | CC_P | CC_A | CC_Z | CC_S | CC_O)
|
||||
|
||||
#define GEN_do_locked_G_E(_name,_eax) \
|
||||
\
|
||||
__attribute__((noinline)) void do_locked_G_E_##_name ( void ) \
|
||||
{ \
|
||||
volatile int e_val, g_val, e_val_before; \
|
||||
int o, s, z, a, c, p, v1, v2, flags_in; \
|
||||
int block[4]; \
|
||||
\
|
||||
for (v1 = 0; v1 < NVALS; v1++) { \
|
||||
for (v2 = 0; v2 < NVALS; v2++) { \
|
||||
\
|
||||
for (o = 0; o < 2; o++) { \
|
||||
for (s = 0; s < 2; s++) { \
|
||||
for (z = 0; z < 2; z++) { \
|
||||
for (a = 0; a < 2; a++) { \
|
||||
for (c = 0; c < 2; c++) { \
|
||||
for (p = 0; p < 2; p++) { \
|
||||
\
|
||||
flags_in = (o ? CC_O : 0) \
|
||||
| (s ? CC_S : 0) \
|
||||
| (z ? CC_Z : 0) \
|
||||
| (a ? CC_A : 0) \
|
||||
| (c ? CC_C : 0) \
|
||||
| (p ? CC_P : 0); \
|
||||
\
|
||||
g_val = val[v1]; \
|
||||
e_val = val[v2]; \
|
||||
e_val_before = e_val; \
|
||||
\
|
||||
block[0] = flags_in; \
|
||||
block[1] = g_val; \
|
||||
block[2] = (int)(long)&e_val; \
|
||||
block[3] = 0; \
|
||||
__asm__ __volatile__( \
|
||||
"movl 0(%0), %%eax\n\t" \
|
||||
"pushl %%eax\n\t" \
|
||||
"popfl\n\t" \
|
||||
"movl 4(%0), %%eax\n\t" \
|
||||
"movl 8(%0), %%ebx\n\t" \
|
||||
"lock; " #_name " %%" #_eax ",(%%ebx)\n\t" \
|
||||
"pushfl\n\t" \
|
||||
"popl %%eax\n\t" \
|
||||
"movl %%eax, 12(%0)\n\t" \
|
||||
: : "r"(&block[0]) : "eax","ebx","cc","memory" \
|
||||
); \
|
||||
\
|
||||
send( \
|
||||
sprintf(outBuf, \
|
||||
"%s G=%08x E=%08x CCIN=%08x -> E=%08x CCOUT=%08x\n", \
|
||||
#_name, g_val, e_val_before, flags_in, \
|
||||
e_val, block[3] & CC_MASK) ); \
|
||||
\
|
||||
}}}}}} \
|
||||
\
|
||||
}} \
|
||||
}
|
||||
|
||||
GEN_do_locked_G_E(addb,al)
|
||||
GEN_do_locked_G_E(addw,ax)
|
||||
GEN_do_locked_G_E(addl,eax)
|
||||
|
||||
GEN_do_locked_G_E(orb, al)
|
||||
GEN_do_locked_G_E(orw, ax)
|
||||
GEN_do_locked_G_E(orl, eax)
|
||||
|
||||
GEN_do_locked_G_E(adcb,al)
|
||||
GEN_do_locked_G_E(adcw,ax)
|
||||
GEN_do_locked_G_E(adcl,eax)
|
||||
|
||||
GEN_do_locked_G_E(sbbb,al)
|
||||
GEN_do_locked_G_E(sbbw,ax)
|
||||
GEN_do_locked_G_E(sbbl,eax)
|
||||
|
||||
GEN_do_locked_G_E(andb,al)
|
||||
GEN_do_locked_G_E(andw,ax)
|
||||
GEN_do_locked_G_E(andl,eax)
|
||||
|
||||
GEN_do_locked_G_E(subb,al)
|
||||
GEN_do_locked_G_E(subw,ax)
|
||||
GEN_do_locked_G_E(subl,eax)
|
||||
|
||||
GEN_do_locked_G_E(xorb,al)
|
||||
GEN_do_locked_G_E(xorw,ax)
|
||||
GEN_do_locked_G_E(xorl,eax)
|
||||
|
||||
|
||||
|
||||
|
||||
#define GEN_do_locked_imm_E(_name,_eax,_imm) \
|
||||
\
|
||||
__attribute__((noinline)) void do_locked_imm_E_##_name##_##_imm ( void ) \
|
||||
{ \
|
||||
volatile int e_val, e_val_before; \
|
||||
int o, s, z, a, c, p, v2, flags_in; \
|
||||
int block[3]; \
|
||||
\
|
||||
for (v2 = 0; v2 < NVALS; v2++) { \
|
||||
\
|
||||
for (o = 0; o < 2; o++) { \
|
||||
for (s = 0; s < 2; s++) { \
|
||||
for (z = 0; z < 2; z++) { \
|
||||
for (a = 0; a < 2; a++) { \
|
||||
for (c = 0; c < 2; c++) { \
|
||||
for (p = 0; p < 2; p++) { \
|
||||
\
|
||||
flags_in = (o ? CC_O : 0) \
|
||||
| (s ? CC_S : 0) \
|
||||
| (z ? CC_Z : 0) \
|
||||
| (a ? CC_A : 0) \
|
||||
| (c ? CC_C : 0) \
|
||||
| (p ? CC_P : 0); \
|
||||
\
|
||||
e_val = val[v2]; \
|
||||
e_val_before = e_val; \
|
||||
\
|
||||
block[0] = flags_in; \
|
||||
block[1] = (int)(long)&e_val; \
|
||||
block[2] = 0; \
|
||||
__asm__ __volatile__( \
|
||||
"movl 0(%0), %%eax\n\t" \
|
||||
"pushl %%eax\n\t" \
|
||||
"popfl\n\t" \
|
||||
"movl 4(%0), %%ebx\n\t" \
|
||||
"lock; " #_name " $" #_imm ",(%%ebx)\n\t" \
|
||||
"pushfl\n\t" \
|
||||
"popl %%eax\n\t" \
|
||||
"movl %%eax, 8(%0)\n\t" \
|
||||
: : "r"(&block[0]) : "eax","ebx","cc","memory" \
|
||||
); \
|
||||
\
|
||||
send( \
|
||||
sprintf(outBuf, \
|
||||
"%s I=%s E=%08x CCIN=%08x -> E=%08x CCOUT=%08x\n", \
|
||||
#_name, #_imm, e_val_before, flags_in, \
|
||||
e_val, block[2] & CC_MASK) ); \
|
||||
\
|
||||
}}}}}} \
|
||||
\
|
||||
} \
|
||||
}
|
||||
|
||||
GEN_do_locked_imm_E(addb,al,0x7F)
|
||||
GEN_do_locked_imm_E(addb,al,0xF1)
|
||||
GEN_do_locked_imm_E(addw,ax,0x7E)
|
||||
GEN_do_locked_imm_E(addw,ax,0x9325)
|
||||
GEN_do_locked_imm_E(addl,eax,0x7D)
|
||||
GEN_do_locked_imm_E(addl,eax,0x31415927)
|
||||
|
||||
GEN_do_locked_imm_E(orb,al,0x7F)
|
||||
GEN_do_locked_imm_E(orb,al,0xF1)
|
||||
GEN_do_locked_imm_E(orw,ax,0x7E)
|
||||
GEN_do_locked_imm_E(orw,ax,0x9325)
|
||||
GEN_do_locked_imm_E(orl,eax,0x7D)
|
||||
GEN_do_locked_imm_E(orl,eax,0x31415927)
|
||||
|
||||
GEN_do_locked_imm_E(adcb,al,0x7F)
|
||||
GEN_do_locked_imm_E(adcb,al,0xF1)
|
||||
GEN_do_locked_imm_E(adcw,ax,0x7E)
|
||||
GEN_do_locked_imm_E(adcw,ax,0x9325)
|
||||
GEN_do_locked_imm_E(adcl,eax,0x7D)
|
||||
GEN_do_locked_imm_E(adcl,eax,0x31415927)
|
||||
|
||||
GEN_do_locked_imm_E(sbbb,al,0x7F)
|
||||
GEN_do_locked_imm_E(sbbb,al,0xF1)
|
||||
GEN_do_locked_imm_E(sbbw,ax,0x7E)
|
||||
GEN_do_locked_imm_E(sbbw,ax,0x9325)
|
||||
GEN_do_locked_imm_E(sbbl,eax,0x7D)
|
||||
GEN_do_locked_imm_E(sbbl,eax,0x31415927)
|
||||
|
||||
GEN_do_locked_imm_E(andb,al,0x7F)
|
||||
GEN_do_locked_imm_E(andb,al,0xF1)
|
||||
GEN_do_locked_imm_E(andw,ax,0x7E)
|
||||
GEN_do_locked_imm_E(andw,ax,0x9325)
|
||||
GEN_do_locked_imm_E(andl,eax,0x7D)
|
||||
GEN_do_locked_imm_E(andl,eax,0x31415927)
|
||||
|
||||
GEN_do_locked_imm_E(subb,al,0x7F)
|
||||
GEN_do_locked_imm_E(subb,al,0xF1)
|
||||
GEN_do_locked_imm_E(subw,ax,0x7E)
|
||||
GEN_do_locked_imm_E(subw,ax,0x9325)
|
||||
GEN_do_locked_imm_E(subl,eax,0x7D)
|
||||
GEN_do_locked_imm_E(subl,eax,0x31415927)
|
||||
|
||||
GEN_do_locked_imm_E(xorb,al,0x7F)
|
||||
GEN_do_locked_imm_E(xorb,al,0xF1)
|
||||
GEN_do_locked_imm_E(xorw,ax,0x7E)
|
||||
GEN_do_locked_imm_E(xorw,ax,0x9325)
|
||||
GEN_do_locked_imm_E(xorl,eax,0x7D)
|
||||
GEN_do_locked_imm_E(xorl,eax,0x31415927)
|
||||
|
||||
#define GEN_do_locked_unary_E(_name,_eax) \
|
||||
\
|
||||
__attribute__((noinline)) void do_locked_unary_E_##_name ( void ) \
|
||||
{ \
|
||||
volatile int e_val, e_val_before; \
|
||||
int o, s, z, a, c, p, v2, flags_in; \
|
||||
int block[3]; \
|
||||
\
|
||||
for (v2 = 0; v2 < NVALS; v2++) { \
|
||||
\
|
||||
for (o = 0; o < 2; o++) { \
|
||||
for (s = 0; s < 2; s++) { \
|
||||
for (z = 0; z < 2; z++) { \
|
||||
for (a = 0; a < 2; a++) { \
|
||||
for (c = 0; c < 2; c++) { \
|
||||
for (p = 0; p < 2; p++) { \
|
||||
\
|
||||
flags_in = (o ? CC_O : 0) \
|
||||
| (s ? CC_S : 0) \
|
||||
| (z ? CC_Z : 0) \
|
||||
| (a ? CC_A : 0) \
|
||||
| (c ? CC_C : 0) \
|
||||
| (p ? CC_P : 0); \
|
||||
\
|
||||
e_val = val[v2]; \
|
||||
e_val_before = e_val; \
|
||||
\
|
||||
block[0] = flags_in; \
|
||||
block[1] = (int)(long)&e_val; \
|
||||
block[2] = 0; \
|
||||
__asm__ __volatile__( \
|
||||
"movl 0(%0), %%eax\n\t" \
|
||||
"pushl %%eax\n\t" \
|
||||
"popfl\n\t" \
|
||||
"movl 4(%0), %%ebx\n\t" \
|
||||
"lock; " #_name " (%%ebx)\n\t" \
|
||||
"pushfl\n\t" \
|
||||
"popl %%eax\n\t" \
|
||||
"movl %%eax, 8(%0)\n\t" \
|
||||
: : "r"(&block[0]) : "eax","ebx","cc","memory" \
|
||||
); \
|
||||
\
|
||||
send( \
|
||||
sprintf(outBuf, \
|
||||
"%s E=%08x CCIN=%08x -> E=%08x CCOUT=%08x\n", \
|
||||
#_name, e_val_before, flags_in, \
|
||||
e_val, block[2] & CC_MASK)); \
|
||||
\
|
||||
}}}}}} \
|
||||
\
|
||||
} \
|
||||
}
|
||||
|
||||
GEN_do_locked_unary_E(decb,al)
|
||||
GEN_do_locked_unary_E(decw,ax)
|
||||
GEN_do_locked_unary_E(decl,eax)
|
||||
|
||||
GEN_do_locked_unary_E(incb,al)
|
||||
GEN_do_locked_unary_E(incw,ax)
|
||||
GEN_do_locked_unary_E(incl,eax)
|
||||
|
||||
GEN_do_locked_unary_E(negb,al)
|
||||
GEN_do_locked_unary_E(negw,ax)
|
||||
GEN_do_locked_unary_E(negl,eax)
|
||||
|
||||
GEN_do_locked_unary_E(notb,al)
|
||||
GEN_do_locked_unary_E(notw,ax)
|
||||
GEN_do_locked_unary_E(notl,eax)
|
||||
|
||||
|
||||
/////////////////////////////////////////////////////////////////
|
||||
|
||||
unsigned int btsl_mem ( UChar* base, int bitno )
|
||||
{
|
||||
unsigned char res;
|
||||
__asm__
|
||||
__volatile__("lock; btsl\t%2, %0\n\t"
|
||||
"setc\t%1"
|
||||
: "=m" (*base), "=q" (res)
|
||||
: "r" (bitno));
|
||||
/* Pretty meaningless to dereference base here, but that's what you
|
||||
have to do to get a btsl insn which refers to memory starting at
|
||||
base. */
|
||||
return res;
|
||||
}
|
||||
unsigned int btsw_mem ( UChar* base, int bitno )
|
||||
{
|
||||
unsigned char res;
|
||||
__asm__
|
||||
__volatile__("lock; btsw\t%w2, %0\n\t"
|
||||
"setc\t%1"
|
||||
: "=m" (*base), "=q" (res)
|
||||
: "r" (bitno));
|
||||
return res;
|
||||
}
|
||||
|
||||
unsigned int btrl_mem ( UChar* base, int bitno )
|
||||
{
|
||||
unsigned char res;
|
||||
__asm__
|
||||
__volatile__("lock; btrl\t%2, %0\n\t"
|
||||
"setc\t%1"
|
||||
: "=m" (*base), "=q" (res)
|
||||
: "r" (bitno));
|
||||
return res;
|
||||
}
|
||||
unsigned int btrw_mem ( UChar* base, int bitno )
|
||||
{
|
||||
unsigned char res;
|
||||
__asm__
|
||||
__volatile__("lock; btrw\t%w2, %0\n\t"
|
||||
"setc\t%1"
|
||||
: "=m" (*base), "=q" (res)
|
||||
: "r" (bitno));
|
||||
return res;
|
||||
}
|
||||
|
||||
unsigned int btcl_mem ( UChar* base, int bitno )
|
||||
{
|
||||
unsigned char res;
|
||||
__asm__
|
||||
__volatile__("lock; btcl\t%2, %0\n\t"
|
||||
"setc\t%1"
|
||||
: "=m" (*base), "=q" (res)
|
||||
: "r" (bitno));
|
||||
return res;
|
||||
}
|
||||
unsigned int btcw_mem ( UChar* base, int bitno )
|
||||
{
|
||||
unsigned char res;
|
||||
__asm__
|
||||
__volatile__("lock; btcw\t%w2, %0\n\t"
|
||||
"setc\t%1"
|
||||
: "=m" (*base), "=q" (res)
|
||||
: "r" (bitno));
|
||||
return res;
|
||||
}
|
||||
|
||||
unsigned int btl_mem ( UChar* base, int bitno )
|
||||
{
|
||||
unsigned char res;
|
||||
__asm__
|
||||
__volatile__("btl\t%2, %0\n\t"
|
||||
"setc\t%1"
|
||||
: "=m" (*base), "=q" (res)
|
||||
: "r" (bitno)
|
||||
: "cc", "memory");
|
||||
return res;
|
||||
}
|
||||
unsigned int btw_mem ( UChar* base, int bitno )
|
||||
{
|
||||
unsigned char res;
|
||||
__asm__
|
||||
__volatile__("btw\t%w2, %0\n\t"
|
||||
"setc\t%1"
|
||||
: "=m" (*base), "=q" (res)
|
||||
: "r" (bitno));
|
||||
return res;
|
||||
}
|
||||
|
||||
ULong rol1 ( ULong x )
|
||||
{
|
||||
return (x << 1) | (x >> 63);
|
||||
}
|
||||
|
||||
void do_bt_G_E_tests ( void )
|
||||
{
|
||||
UInt n, bitoff, op;
|
||||
UInt c;
|
||||
UChar* block;
|
||||
ULong carrydep, res;;
|
||||
|
||||
/*------------------------ MEM-L -----------------------*/
|
||||
|
||||
carrydep = 0;
|
||||
block = calloc(200,1);
|
||||
block += 100;
|
||||
/* Valid bit offsets are -800 .. 799 inclusive. */
|
||||
|
||||
for (n = 0; n < 10000; n++) {
|
||||
bitoff = (random() % 1600) - 800;
|
||||
op = random() % 4;
|
||||
c = 2;
|
||||
switch (op) {
|
||||
case 0: c = btsl_mem(block, bitoff); break;
|
||||
case 1: c = btrl_mem(block, bitoff); break;
|
||||
case 2: c = btcl_mem(block, bitoff); break;
|
||||
case 3: c = btl_mem(block, bitoff); break;
|
||||
}
|
||||
c &= 255;
|
||||
assert(c == 0 || c == 1);
|
||||
carrydep = c ? (rol1(carrydep) ^ (Long)(Int)bitoff) : carrydep;
|
||||
}
|
||||
|
||||
/* Compute final result */
|
||||
block -= 100;
|
||||
res = 0;
|
||||
for (n = 0; n < 200; n++) {
|
||||
UChar ch = block[n];
|
||||
/* printf("%d ", (int)block[n]); */
|
||||
res = rol1(res) ^ (ULong)ch;
|
||||
}
|
||||
|
||||
send( sprintf(outBuf,
|
||||
"bt{s,r,c}l: final res 0x%llx, carrydep 0x%llx\n",
|
||||
res, carrydep ));
|
||||
free(block);
|
||||
|
||||
/*------------------------ MEM-W -----------------------*/
|
||||
|
||||
carrydep = 0;
|
||||
block = calloc(200,1);
|
||||
block += 100;
|
||||
/* Valid bit offsets are -800 .. 799 inclusive. */
|
||||
|
||||
for (n = 0; n < 10000; n++) {
|
||||
bitoff = (random() % 1600) - 800;
|
||||
op = random() % 4;
|
||||
c = 2;
|
||||
switch (op) {
|
||||
case 0: c = btsw_mem(block, bitoff); break;
|
||||
case 1: c = btrw_mem(block, bitoff); break;
|
||||
case 2: c = btcw_mem(block, bitoff); break;
|
||||
case 3: c = btw_mem(block, bitoff); break;
|
||||
}
|
||||
c &= 255;
|
||||
assert(c == 0 || c == 1);
|
||||
carrydep = c ? (rol1(carrydep) ^ (Long)(Int)bitoff) : carrydep;
|
||||
}
|
||||
|
||||
/* Compute final result */
|
||||
block -= 100;
|
||||
res = 0;
|
||||
for (n = 0; n < 200; n++) {
|
||||
UChar ch = block[n];
|
||||
/* printf("%d ", (int)block[n]); */
|
||||
res = rol1(res) ^ (ULong)ch;
|
||||
}
|
||||
|
||||
send( sprintf(outBuf,
|
||||
"bt{s,r,c}w: final res 0x%llx, carrydep 0x%llx\n",
|
||||
res, carrydep ));
|
||||
free(block);
|
||||
}
|
||||
|
||||
|
||||
/////////////////////////////////////////////////////////////////
|
||||
|
||||
/* Given a word, do bt/bts/btr/btc on bits 0, 1, 2 and 3 of it, and
|
||||
also reconstruct the original bits 0, 1, 2, 3 by looking at the
|
||||
carry flag. Returned result has mashed bits 0-3 at the bottom and
|
||||
the reconstructed original bits 0-3 as 4-7. */
|
||||
|
||||
UInt mash_mem_L ( UInt* origp )
|
||||
{
|
||||
UInt reconstructed, mashed;
|
||||
__asm__ __volatile__ (
|
||||
"movl %2, %%edx\n\t"
|
||||
""
|
||||
"movl $0, %%eax\n\t"
|
||||
"\n\t"
|
||||
"btl $0, (%%edx)\n\t"
|
||||
"setb %%cl\n\t"
|
||||
"movzbl %%cl, %%ecx\n\t"
|
||||
"orl %%ecx, %%eax\n\t"
|
||||
"\n\t"
|
||||
"lock; btsl $1, (%%edx)\n\t"
|
||||
"setb %%cl\n\t"
|
||||
"movzbl %%cl, %%ecx\n\t"
|
||||
"shll $1, %%ecx\n\t"
|
||||
"orl %%ecx, %%eax\n\t"
|
||||
"\n\t"
|
||||
"lock; btrl $2, (%%edx)\n\t"
|
||||
"setb %%cl\n\t"
|
||||
"movzbl %%cl, %%ecx\n\t"
|
||||
"shll $2, %%ecx\n\t"
|
||||
"orl %%ecx, %%eax\n\t"
|
||||
"\n\t"
|
||||
"lock; btcl $3, (%%edx)\n\t"
|
||||
"setb %%cl\n\t"
|
||||
"movzbl %%cl, %%ecx\n\t"
|
||||
"shll $3, %%ecx\n\t"
|
||||
"orl %%ecx, %%eax\n\t"
|
||||
"\n\t"
|
||||
"movl %%eax, %0\n\t"
|
||||
"movl (%%edx), %1"
|
||||
|
||||
: "=r" (reconstructed), "=r" (mashed)
|
||||
: "r" (origp)
|
||||
: "eax", "ecx", "edx", "cc");
|
||||
return (mashed & 0xF) | ((reconstructed & 0xF) << 4);
|
||||
}
|
||||
|
||||
UInt mash_mem_W ( UShort* origp )
|
||||
{
|
||||
UInt reconstructed, mashed;
|
||||
__asm__ __volatile__ (
|
||||
"movl %2, %%edx\n\t"
|
||||
""
|
||||
"movl $0, %%eax\n\t"
|
||||
"\n\t"
|
||||
"btw $0, (%%edx)\n\t"
|
||||
"setb %%cl\n\t"
|
||||
"movzbl %%cl, %%ecx\n\t"
|
||||
"orl %%ecx, %%eax\n\t"
|
||||
"\n\t"
|
||||
"lock; btsw $1, (%%edx)\n\t"
|
||||
"setb %%cl\n\t"
|
||||
"movzbl %%cl, %%ecx\n\t"
|
||||
"shll $1, %%ecx\n\t"
|
||||
"orl %%ecx, %%eax\n\t"
|
||||
"\n\t"
|
||||
"lock; btrw $2, (%%edx)\n\t"
|
||||
"setb %%cl\n\t"
|
||||
"movzbl %%cl, %%ecx\n\t"
|
||||
"shll $2, %%ecx\n\t"
|
||||
"orl %%ecx, %%eax\n\t"
|
||||
"\n\t"
|
||||
"lock; btcw $3, (%%edx)\n\t"
|
||||
"setb %%cl\n\t"
|
||||
"movzbl %%cl, %%ecx\n\t"
|
||||
"shll $3, %%ecx\n\t"
|
||||
"orl %%ecx, %%eax\n\t"
|
||||
"\n\t"
|
||||
"movl %%eax, %0\n\t"
|
||||
"movzwl (%%edx), %1"
|
||||
|
||||
: "=r" (reconstructed), "=r" (mashed)
|
||||
: "r" (origp)
|
||||
: "eax", "ecx", "edx", "cc");
|
||||
return (mashed & 0xF) | ((reconstructed & 0xF) << 4);
|
||||
}
|
||||
|
||||
|
||||
void do_bt_imm_E_tests( void )
|
||||
{
|
||||
int i;
|
||||
UInt* iil = malloc(sizeof(UInt));
|
||||
UShort* iiw = malloc(sizeof(UShort));
|
||||
for (i = 0; i < 0x10; i++) {
|
||||
*iil = i;
|
||||
*iiw = i;
|
||||
send( sprintf(outBuf, "0x%x -> 0x%02x 0x%02x\n", i,
|
||||
mash_mem_L(iil), mash_mem_W(iiw)));
|
||||
}
|
||||
free(iil);
|
||||
free(iiw);
|
||||
}
|
||||
|
||||
|
||||
|
||||
/////////////////////////////////////////////////////////////////
|
||||
|
||||
int main ( void )
|
||||
{
|
||||
do_locked_G_E_addb();
|
||||
do_locked_G_E_addw();
|
||||
do_locked_G_E_addl();
|
||||
|
||||
do_locked_G_E_orb();
|
||||
do_locked_G_E_orw();
|
||||
do_locked_G_E_orl();
|
||||
|
||||
do_locked_G_E_adcb();
|
||||
do_locked_G_E_adcw();
|
||||
do_locked_G_E_adcl();
|
||||
|
||||
do_locked_G_E_sbbb();
|
||||
do_locked_G_E_sbbw();
|
||||
do_locked_G_E_sbbl();
|
||||
|
||||
do_locked_G_E_andb();
|
||||
do_locked_G_E_andw();
|
||||
do_locked_G_E_andl();
|
||||
|
||||
do_locked_G_E_subb();
|
||||
do_locked_G_E_subw();
|
||||
do_locked_G_E_subl();
|
||||
|
||||
do_locked_G_E_xorb();
|
||||
do_locked_G_E_xorw();
|
||||
do_locked_G_E_xorl();
|
||||
//21
|
||||
do_locked_imm_E_addb_0x7F();
|
||||
do_locked_imm_E_addb_0xF1();
|
||||
do_locked_imm_E_addw_0x7E();
|
||||
do_locked_imm_E_addw_0x9325();
|
||||
do_locked_imm_E_addl_0x7D();
|
||||
do_locked_imm_E_addl_0x31415927();
|
||||
|
||||
do_locked_imm_E_orb_0x7F();
|
||||
do_locked_imm_E_orb_0xF1();
|
||||
do_locked_imm_E_orw_0x7E();
|
||||
do_locked_imm_E_orw_0x9325();
|
||||
do_locked_imm_E_orl_0x7D();
|
||||
do_locked_imm_E_orl_0x31415927();
|
||||
|
||||
do_locked_imm_E_adcb_0x7F();
|
||||
do_locked_imm_E_adcb_0xF1();
|
||||
do_locked_imm_E_adcw_0x7E();
|
||||
do_locked_imm_E_adcw_0x9325();
|
||||
do_locked_imm_E_adcl_0x7D();
|
||||
do_locked_imm_E_adcl_0x31415927();
|
||||
|
||||
do_locked_imm_E_sbbb_0x7F();
|
||||
do_locked_imm_E_sbbb_0xF1();
|
||||
do_locked_imm_E_sbbw_0x7E();
|
||||
do_locked_imm_E_sbbw_0x9325();
|
||||
do_locked_imm_E_sbbl_0x7D();
|
||||
do_locked_imm_E_sbbl_0x31415927();
|
||||
|
||||
do_locked_imm_E_andb_0x7F();
|
||||
do_locked_imm_E_andb_0xF1();
|
||||
do_locked_imm_E_andw_0x7E();
|
||||
do_locked_imm_E_andw_0x9325();
|
||||
do_locked_imm_E_andl_0x7D();
|
||||
do_locked_imm_E_andl_0x31415927();
|
||||
|
||||
do_locked_imm_E_subb_0x7F();
|
||||
do_locked_imm_E_subb_0xF1();
|
||||
do_locked_imm_E_subw_0x7E();
|
||||
do_locked_imm_E_subw_0x9325();
|
||||
do_locked_imm_E_subl_0x7D();
|
||||
do_locked_imm_E_subl_0x31415927();
|
||||
|
||||
do_locked_imm_E_xorb_0x7F();
|
||||
do_locked_imm_E_xorb_0xF1();
|
||||
do_locked_imm_E_xorw_0x7E();
|
||||
do_locked_imm_E_xorw_0x9325();
|
||||
do_locked_imm_E_xorl_0x7D();
|
||||
do_locked_imm_E_xorl_0x31415927();
|
||||
// 63
|
||||
do_locked_unary_E_decb();
|
||||
do_locked_unary_E_decw();
|
||||
do_locked_unary_E_decl();
|
||||
|
||||
do_locked_unary_E_incb();
|
||||
do_locked_unary_E_incw();
|
||||
do_locked_unary_E_incl();
|
||||
|
||||
do_locked_unary_E_negb();
|
||||
do_locked_unary_E_negw();
|
||||
do_locked_unary_E_negl();
|
||||
|
||||
do_locked_unary_E_notb();
|
||||
do_locked_unary_E_notw();
|
||||
do_locked_unary_E_notl();
|
||||
// 75
|
||||
do_bt_G_E_tests();
|
||||
// 81
|
||||
do_bt_imm_E_tests();
|
||||
// 87
|
||||
// So there should be 87 lock-prefixed instructions in the
|
||||
// disassembly of this compilation unit.
|
||||
// confirm with
|
||||
// objdump -d ./x86locked | grep lock | grep -v do_lock | grep -v elf32 | wc
|
||||
|
||||
{ UInt crcExpd = 0x8235DC9C;
|
||||
theCRC = crcFinalise( theCRC );
|
||||
if (theCRC == crcExpd) {
|
||||
printf("x86locked: PASS: CRCs actual 0x%08X expected 0x%08X\n",
|
||||
theCRC, crcExpd);
|
||||
} else {
|
||||
printf("x86locked: FAIL: CRCs actual 0x%08X expected 0x%08X\n",
|
||||
theCRC, crcExpd);
|
||||
printf("x86locked: set #define VERBOSE 1 to diagnose\n");
|
||||
}
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
2
none/tests/x86/x86locked.stderr.exp
Normal file
2
none/tests/x86/x86locked.stderr.exp
Normal file
@ -0,0 +1,2 @@
|
||||
|
||||
|
||||
1
none/tests/x86/x86locked.stdout.exp
Normal file
1
none/tests/x86/x86locked.stdout.exp
Normal file
@ -0,0 +1 @@
|
||||
x86locked: PASS: CRCs actual 0x8235DC9C expected 0x8235DC9C
|
||||
1
none/tests/x86/x86locked.vgtest
Normal file
1
none/tests/x86/x86locked.vgtest
Normal file
@ -0,0 +1 @@
|
||||
prog: x86locked
|
||||
Loading…
x
Reference in New Issue
Block a user