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PowerPC:, Update test test_isa_3_1_R1_RT.c, test_isa_3_1_R1_XT.c

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The commit:

  commit 20cc0680c3491e062c76605b24e76dc02e16ef47
  Author: Carl Love <cel@us.ibm.com>
  Date:   Mon Apr 17 17:12:25 2023 -0400

      PowerPC:, Fix test test_isa_3_1_R1_RT.c, test_isa_3_1_R1_XT.c

Fixes an issue with the PAD_ORI used in the the tests by explicitly adding
SAVE_REGS and RESTORE_REGS macros.  The macros ensure that the block of
immediate OR instructions don't inadvertently change the contents of the
registers.

John Reiser suggested that the PAD_ORI asm statements in the PAD_ORI
macro be updated to inform the compiler which register the ori instruction
is clobbering.  The compiler will then generate the code to save and
restore the register automatically.  This is a cleaner solution then
explicitly adding the macros to store and restore the registers.  It is
functionally cleaner in that the value fetched by the instruction under
test is not modified by the PAD_ORI instructions.

This patch removes the SAVE_REG and RESTORE_REG macros and updates the
PAD_ORI macro.
This commit is contained in:
Carl Love 2023-04-19 13:45:19 -04:00
parent b0e9fef201
commit 19c9e2418c
5 changed files with 52 additions and 451 deletions
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40
none/tests/ppc64/isa_3_1_helpers.h
View File

@ -67,14 +67,38 @@ extern void initialize_buffer(int);
#define RELOC_BUFFER_SIZE 0x1000
extern unsigned long long pcrelative_buff_addr(int);
#define PAD_ORI \
__asm__ __volatile__ ("ori 21,21,21"); \
__asm__ __volatile__ ("ori 22,22,22");\
__asm__ __volatile__ ("ori 23,23,23");\
__asm__ __volatile__ ("ori 24,24,24");\
__asm__ __volatile__ ("ori 25,25,25");\
__asm__ __volatile__ ("ori 26,26,26");\
__asm__ __volatile__ ("ori 27,27,27");\
__asm__ __volatile__ ("ori 28,28,28");
__asm__ __volatile__ ("ori 21,21,21" \
: /* empty: no outputs from asm to C */ \
: /* empty: no inputs from C to asm */ \
: "21" /* clobbers register 21 */); \
__asm__ __volatile__ ("ori 22,22,22" \
: /* empty: no outputs from asm to C */ \
: /* empty: no inputs from C to asm */ \
: "22" /* clobbers register 22 */); \
__asm__ __volatile__ ("ori 23,23,23" \
: /* empty: no outputs from asm to C */ \
: /* empty: no inputs from C to asm */ \
: "23" /* clobbers register 23 */); \
__asm__ __volatile__ ("ori 24,24,24" \
: /* empty: no outputs from asm to C */ \
: /* empty: no inputs from C to asm */ \
: "24" /* clobbers register 24 */); \
__asm__ __volatile__ ("ori 25,25,25" \
: /* empty: no outputs from asm to C */ \
: /* empty: no inputs from C to asm */ \
: "25" /* clobbers register 25 */); \
__asm__ __volatile__ ("ori 26,26,26" \
: /* empty: no outputs from asm to C */ \
: /* empty: no inputs from C to asm */ \
: "26" /* clobbers register 26 */); \
__asm__ __volatile__ ("ori 27,27,27" \
: /* empty: no outputs from asm to C */ \
: /* empty: no inputs from C to asm */ \
: "27" /* clobbers register 27 */); \
__asm__ __volatile__ ("ori 28,28,28" \
: /* empty: no outputs from asm to C */ \
: /* empty: no inputs from C to asm */ \
: "28" /* clobbers register 28 */);
extern int verbose;
#define debug_printf(X) if (verbose>0) printf(X);

246
none/tests/ppc64/test_isa_3_1_R1_RT.c
View File

@ -49,304 +49,108 @@ struct test_list_t current_test;
#include "isa_3_1_helpers.h"
#ifdef __powerpc64__
typedef uint64_t HWord_t;
/* Save and restore all of the registers but rt which is the result of the instruction
under test. Need to ensure the PAD_ORI does not change the other registers. This
really shouldn't be needed but the optimization gets messed up when it inlines the
test function. */
#define SAVE_REGS(addr) \
asm volatile( \
" std 21, 0(%0) \n" \
" std 22, 8(%0) \n" \
" std 23, 16(%0) \n" \
" std 24, 24(%0) \n" \
" std 25, 32(%0) \n" \
" std 28, 56(%0) \n" \
" std 29, 64(%0) \n" \
" std 30, 72(%0) \n" \
" std 31, 80(%0) \n" \
::"b"(addr))
#define SAVE_REG_RT(addr) \
asm volatile( \
" std 26, 40(%0) \n" \
::"b"(addr))
#define SAVE_REG_27(addr) \
asm volatile( \
" std 27, 40(%0) \n" \
::"b"(addr))
#define RESTORE_REGS(addr) \
asm volatile( \
" ld 21, 0(%0) \n" \
" ld 22, 8(%0) \n" \
" ld 23, 16(%0) \n" \
" ld 24, 24(%0) \n" \
" ld 25, 32(%0) \n" \
" ld 28, 56(%0) \n" \
" ld 29, 64(%0) \n" \
" ld 30, 72(%0) \n" \
" ld 31, 80(%0) \n" \
::"b"(addr))
#define RESTORE_REG_RT(addr) \
asm volatile( \
" ld 26, 40(%0) \n" \
::"b"(addr))
#define RESTORE_REG_27(addr) \
asm volatile( \
" ld 27, 40(%0) \n" \
::"b"(addr))
#else /* !__powerpc64__ */
typedef uint32_t HWord_t;
#define SAVE_REGS(addr) \
asm volatile( \
" stw 21, 0(%0) \n" \
" stw 22, 4(%0) \n" \
" stw 23, 8(%0) \n" \
" stw 24, 12(%0) \n" \
" stw 25, 16(%0) \n" \
" stw 28, 28(%0) \n" \
" stw 29, 32(%0) \n" \
" stw 30, 36(%0) \n" \
" stw 31, 40(%0) \n" \
::"b"(addr))
#define SAVE_REG_RT(addr) \
asm volatile( \
" stw 26, 20(%0) \n" \
::"b"(addr))
#define SAVE_REG_27(addr) \
asm volatile( \
" stw 27, 20(%0) \n" \
::"b"(addr))
#define RESTORE_REGS(addr) \
asm volatile( \
" lwz 21, 0(%0) \n" \
" lwz 22, 4(%0) \n" \
" lwz 23, 8(%0) \n" \
" lwz 24, 12(%0) \n" \
" lwz 25, 16(%0) \n" \
" lwz 28, 28(%0) \n" \
" lwz 29, 32(%0) \n" \
" lwz 30, 36(%0) \n" \
" lwz 31, 400(%0) \n" \
::"b"(addr))
#define RESTORE_REG_RT(addr) \
asm volatile( \
" lwz 26, 40(%0) \n" \
::"b"(addr))
#define RESTORE_REG_27(addr) \
asm volatile( \
" lwz 27, 40(%0) \n" \
::"b"(addr))
#endif /* __powerpc64__ */
#define NUM_ENTRIES_SAVE_RESTORE 11
HWord_t temp[NUM_ENTRIES_SAVE_RESTORE];
static void test_plxvp_off0_R1 (void) {
SAVE_REGS(temp);
SAVE_REG_RT(temp);
SAVE_REG_27(temp);
PAD_ORI
__asm__ __volatile__ ("plxvp 20, +0(0),1" );
PAD_ORI
RESTORE_REGS(temp);
RESTORE_REG_RT(temp);
RESTORE_REG_27(temp);
}
static void test_plxvp_off8_R1 (void) {
SAVE_REGS(temp);
SAVE_REG_RT(temp);
SAVE_REG_27(temp);
PAD_ORI
__asm__ __volatile__ ("plxvp 20, +8(0),1" );
PAD_ORI
RESTORE_REGS(temp);
RESTORE_REG_RT(temp);
RESTORE_REG_27(temp);
}
static void test_plxvp_off16_R1 (void) {
SAVE_REGS(temp);
SAVE_REG_RT(temp);
SAVE_REG_27(temp);
PAD_ORI
__asm__ __volatile__ ("plxvp 20, +16(0),1" );
PAD_ORI
RESTORE_REGS(temp);
RESTORE_REG_RT(temp);
RESTORE_REG_27(temp);
}
static void test_plxvp_off24_R1 (void) {
SAVE_REGS(temp);
SAVE_REG_RT(temp);
SAVE_REG_27(temp);
PAD_ORI
__asm__ __volatile__ ("plxvp 20, +24(0),1" );
PAD_ORI
RESTORE_REGS(temp);
RESTORE_REG_RT(temp);
RESTORE_REG_27(temp);
}
static void test_plxvp_off32_R1 (void) {
SAVE_REGS(temp);
SAVE_REG_RT(temp);
SAVE_REG_27(temp);
PAD_ORI
__asm__ __volatile__ ("plxvp 20, +32(0),1" );
PAD_ORI
RESTORE_REGS(temp);
RESTORE_REG_RT(temp);
RESTORE_REG_27(temp);
}
static void test_plbz_off0_R1 (void) {
SAVE_REGS(temp);
SAVE_REG_27(temp);
PAD_ORI
__asm__ __volatile__ ("plbz %0, +0(0), 1" : "=r" (rt) );
PAD_ORI
RESTORE_REGS(temp);
RESTORE_REG_27(temp);
}
static void test_plbz_off8_R1 (void) {
SAVE_REGS(temp);
SAVE_REG_27(temp);
PAD_ORI
__asm__ __volatile__ ("plbz %0, +8(0), 1" : "=r" (rt) );
PAD_ORI
RESTORE_REGS(temp);
RESTORE_REG_27(temp);
}
static void test_plbz_off16_R1 (void) {
SAVE_REGS(temp);
SAVE_REG_27(temp);
PAD_ORI
__asm__ __volatile__ ("plbz %0, +16(0), 1" : "=r" (rt) );
PAD_ORI
RESTORE_REGS(temp);
RESTORE_REG_27(temp);
}
static void test_plbz_off32_R1 (void) {
SAVE_REGS(temp);
SAVE_REG_27(temp);
PAD_ORI
__asm__ __volatile__ ("plbz %0, +32(0), 1" : "=r" (rt) );
PAD_ORI
RESTORE_REGS(temp);
RESTORE_REG_27(temp);
}
static void test_plbz_off64_R1 (void) {
SAVE_REGS(temp);
SAVE_REG_27(temp);
PAD_ORI
__asm__ __volatile__ ("plbz %0, +64(0), 1" : "=r" (rt) );
PAD_ORI
PAD_ORI
RESTORE_REGS(temp);
RESTORE_REG_27(temp);
}
static void test_plhz_off0_R1 (void) {
SAVE_REGS(temp);
SAVE_REG_27(temp);
PAD_ORI
__asm__ __volatile__ ("plhz %0, +0(0), 1" : "=r" (rt) );
PAD_ORI
RESTORE_REGS(temp);
RESTORE_REG_27(temp);
}
static void test_plhz_off8_R1 (void) {
SAVE_REGS(temp);
SAVE_REG_27(temp);
PAD_ORI
__asm__ __volatile__ ("plhz %0, +8(0), 1" : "=r" (rt) );
PAD_ORI
RESTORE_REGS(temp);
RESTORE_REG_27(temp);
}
static void test_plhz_off16_R1 (void) {
SAVE_REGS(temp);
SAVE_REG_27(temp);
PAD_ORI
__asm__ __volatile__ ("plhz %0, +16(0), 1" : "=r" (rt) );
PAD_ORI
RESTORE_REGS(temp);
RESTORE_REG_27(temp);
}
static void test_plhz_off32_R1 (void) {
SAVE_REGS(temp);
SAVE_REG_27(temp);
PAD_ORI
__asm__ __volatile__ ("plhz %0, +32(0), 1" : "=r" (rt) );
PAD_ORI
RESTORE_REGS(temp);
RESTORE_REG_27(temp);
}
static void test_plhz_off64_R1 (void) {
SAVE_REGS(temp);
SAVE_REG_27(temp);
PAD_ORI
__asm__ __volatile__ ("plhz %0, +64(0), 1" : "=r" (rt) );
PAD_ORI
PAD_ORI
RESTORE_REGS(temp);
RESTORE_REG_27(temp);
}
static void test_plha_off0_R1 (void) {
SAVE_REGS(temp);
SAVE_REG_27(temp);
PAD_ORI
__asm__ __volatile__ ("plha %0, +0(0), 1" : "=r" (rt) );
PAD_ORI
RESTORE_REGS(temp);
RESTORE_REG_27(temp);
}
static void test_plha_off8_R1 (void) {
SAVE_REGS(temp);
SAVE_REG_27(temp);
PAD_ORI
__asm__ __volatile__ ("plha %0, +8(0), 1" : "=r" (rt) );
PAD_ORI
RESTORE_REGS(temp);
RESTORE_REG_27(temp);
}
static void test_plha_off16_R1 (void) {
SAVE_REGS(temp);
SAVE_REG_27(temp);
PAD_ORI
__asm__ __volatile__ ("plha %0, +16(0), 1" : "=r" (rt) );
PAD_ORI
RESTORE_REGS(temp);
RESTORE_REG_27(temp);
}
static void test_plha_off32_R1 (void) {
SAVE_REGS(temp);
SAVE_REG_27(temp);
PAD_ORI
__asm__ __volatile__ ("plha %0, +32(0), 1" : "=r" (rt) );
PAD_ORI
RESTORE_REGS(temp);
RESTORE_REG_27(temp);
}
static void test_plha_off64_R1 (void) {
SAVE_REGS(temp);
SAVE_REG_27(temp);
PAD_ORI
__asm__ __volatile__ ("plha %0, +64(0), 1" : "=r" (rt) );
PAD_ORI
PAD_ORI
RESTORE_REG_27(temp);
RESTORE_REGS(temp);
}
static void test_plwz_off0_R1 (void) {
__asm__ __volatile__ ("plwz %0, +0(0), 1" : "=r" (rt) );
@ -358,23 +162,15 @@ static void test_plwz_off16_R1 (void) {
__asm__ __volatile__ ("plwz %0, +16(0), 1" : "=r" (rt) );
}
static void test_plwz_off32_R1 (void) {
SAVE_REGS(temp);
SAVE_REG_27(temp);
PAD_ORI
__asm__ __volatile__ ("plwz %0, +32(0), 1" : "=r" (rt) );
PAD_ORI
RESTORE_REGS(temp);
RESTORE_REG_27(temp);
}
static void test_plwz_off64_R1 (void) {
SAVE_REGS(temp);
SAVE_REG_27(temp);
PAD_ORI
__asm__ __volatile__ ("plwz %0, +64(0), 1" : "=r" (rt) );
PAD_ORI
PAD_ORI
RESTORE_REGS(temp);
RESTORE_REG_27(temp);
}
static void test_plwa_off0_R1 (void) {
__asm__ __volatile__ ("plwa %0, +0(0), 1" : "=r" (rt) );
@ -386,69 +182,41 @@ static void test_plwa_off16_R1 (void) {
__asm__ __volatile__ ("plwa %0, +16(0), 1" : "=r" (rt) );
}
static void test_plwa_off32_R1 (void) {
SAVE_REGS(temp);
SAVE_REG_27(temp);
PAD_ORI
__asm__ __volatile__ ("plwa %0, +32(0), 1" : "=r" (rt) );
PAD_ORI
RESTORE_REGS(temp);
RESTORE_REG_27(temp);
}
static void test_plwa_off64_R1 (void) {
SAVE_REGS(temp);
SAVE_REG_27(temp);
PAD_ORI
__asm__ __volatile__ ("plwa %0, +64(0), 1" : "=r" (rt) );
PAD_ORI
PAD_ORI
RESTORE_REGS(temp);
RESTORE_REG_27(temp);
}
static void test_pld_off0_R1 (void) {
SAVE_REGS(temp);
SAVE_REG_27(temp);
PAD_ORI
__asm__ __volatile__ ("pld %0, +0(0), 1" : "=r" (rt) );
PAD_ORI
RESTORE_REGS(temp);
RESTORE_REG_27(temp);
}
static void test_pld_off8_R1 (void) {
SAVE_REGS(temp);
SAVE_REG_27(temp);
PAD_ORI
__asm__ __volatile__ ("pld %0, +8(0), 1" : "=r" (rt) );
PAD_ORI
RESTORE_REGS(temp);
RESTORE_REG_27(temp);
}
static void test_pld_off16_R1 (void) {
SAVE_REGS(temp);
SAVE_REG_27(temp);
PAD_ORI
__asm__ __volatile__ ("pld %0, +16(0), 1" : "=r" (rt) );
PAD_ORI
RESTORE_REGS(temp);
RESTORE_REG_27(temp);
}
static void test_pld_off32_R1 (void) {
SAVE_REGS(temp);
SAVE_REG_27(temp);
PAD_ORI
__asm__ __volatile__ ("pld %0, +32(0), 1" : "=r" (rt) );
PAD_ORI
RESTORE_REGS(temp);
RESTORE_REG_27(temp);
}
static void test_pld_off64_R1 (void) {
SAVE_REGS(temp);
SAVE_REG_27(temp);
PAD_ORI
__asm__ __volatile__ ("pld %0, +64(0), 1" : "=r" (rt) );
PAD_ORI
PAD_ORI
RESTORE_REGS(temp);
RESTORE_REG_27(temp);
}
static void test_pstb_off0_R1 (void) {
__asm__ __volatile__ ("pstb %0, -0x1f400+0(0), 1" :: "r" (rs) );
@ -534,49 +302,35 @@ static void test_paddi_98_R1 (void) {
rt = 0xffff0098;
}
static void test_plq_off0_R1 (void) {
SAVE_REGS(temp);
PAD_ORI
__asm__ __volatile__ ("plq %0, +0(0), 1" : "=r" (rt) );
PAD_ORI
RESTORE_REGS(temp);
}
static void test_plq_off8_R1 (void) {
SAVE_REGS(temp);
PAD_ORI
__asm__ __volatile__ ("plq %0, +8(0), 1" : "=r" (rt) );
PAD_ORI
RESTORE_REGS(temp);
}
static void test_plq_off16_R1 (void) {
SAVE_REGS(temp);
PAD_ORI
__asm__ __volatile__ ("plq %0, +16(0), 1" : "=r" (rt) );
PAD_ORI
RESTORE_REGS(temp);
}
static void test_plq_off32_R1 (void) {
SAVE_REGS(temp);
PAD_ORI
__asm__ __volatile__ ("plq %0, +32(0), 1" : "=r" (rt) );
PAD_ORI
RESTORE_REGS(temp);
}
static void test_plq_off48_R1 (void) {
SAVE_REGS(temp);
PAD_ORI
__asm__ __volatile__ ("plq %0, +48(0), 1" : "=r" (rt) );
PAD_ORI
RESTORE_REGS(temp);
}
static void test_plq_off64_R1 (void) {
SAVE_REGS(temp);
SAVE_REG_RT(temp);
PAD_ORI
__asm__ __volatile__ ("plq %0, +64(0), 1" : "=r" (rt) );
PAD_ORI
PAD_ORI
RESTORE_REGS(temp);
RESTORE_REG_RT(temp);
}
static void test_pstq_off0_R1 (void) {
__asm__ __volatile__ ("pstq 24, -0x1f400+0(0), 1" );

12
none/tests/ppc64/test_isa_3_1_R1_RT.stdout.exp
View File

@ -52,11 +52,11 @@ plq off8_R1 => 62d6001662b5001f 6318001862f7001f
plq off16_R1 => 6318001862f7001f 635a001a6339001b
plq off32_R1 => 639c001c637b001b eac90008eaa9001b
plq off32_R1 => 639c001c637b001b eb81ffe0eae1ffbb
plq off48_R1 => eb090018eae9001a eb890038eb29003b
plq off48_R1 => 4e80003a 9000000001b
plq off64_R1 => 1111111111111111 eac90008eaa9001b
plq off64_R1 => 639c001c637b001b eb81ffe0eae1ffbb
plwa off0_R1 => 4100000
@ -82,11 +82,11 @@ plxvp off0_R1 => 6318001862f70017 635a001a63390019 ea80000004100000 62d6001662b5
plxvp off8_R1 => 635a001a63390019 639c001c637b001b 62d6001662b50015 6318001862f70017
plxvp off16_R1 => 639c001c637b001b eac90008eaa90000 6318001862f70017 635a001a63390019
plxvp off16_R1 => 639c001c637b001b eb81ffe0eae1ffb8 6318001862f70017 635a001a63390019
plxvp off24_R1 => eac90008eaa90000 eb090018eae90010 635a001a63390019 639c001c637b001b
plxvp off24_R1 => eb81ffe0eae1ffb8 000000004e800020 635a001a63390019 639c001c637b001b
plxvp off32_R1 => eb090018eae90010 eb890038eb290020 639c001c637b001b eac90008eaa90000
plxvp off32_R1 => 000000004e800020 0000090000000000 639c001c637b001b eb81ffe0eae1ffb8
pstb off0_R1 102030405060708 => 08

177
none/tests/ppc64/test_isa_3_1_R1_XT.c
View File

@ -48,95 +48,6 @@ unsigned long current_fpscr;
struct test_list_t current_test;
#include "isa_3_1_helpers.h"
#ifdef __powerpc64__
typedef uint64_t HWord_t;
/* Save and restore all of the registers. Need to ensure the PAD_ORI does not change
the other registers. This really shouldn't be needed but the optimization gets
messed up when it inlines the test function. */
#define SAVE_REGS(addr) \
asm volatile( \
" std 21, 0(%0) \n" \
" std 22, 8(%0) \n" \
" std 23, 16(%0) \n" \
" std 24, 24(%0) \n" \
" std 25, 32(%0) \n" \
" std 26, 40(%0) \n" \
" std 27, 48(%0) \n" \
" std 29, 64(%0) \n" \
" std 30, 72(%0) \n" \
" std 31, 80(%0) \n" \
::"b"(addr))
#define SAVE_REG_28(addr) \
asm volatile( \
" std 28, 56(%0) \n" \
::"b"(addr))
#define RESTORE_REGS(addr) \
asm volatile( \
" ld 21, 0(%0) \n" \
" ld 22, 8(%0) \n" \
" ld 23, 16(%0) \n" \
" ld 24, 24(%0) \n" \
" ld 25, 32(%0) \n" \
" ld 26, 40(%0) \n" \
" ld 27, 48(%0) \n" \
" ld 29, 64(%0) \n" \
" ld 30, 72(%0) \n" \
" ld 31, 80(%0) \n" \
::"b"(addr))
#define RESTORE_REG_28(addr) \
asm volatile( \
" ld 28, 56(%0) \n" \
::"b"(addr))
#else /* !__powerpc64__ */
typedef uint32_t HWord_t;
#define SAVE_REGS(addr) \
asm volatile( \
" stw 21, 0(%0) \n" \
" stw 22, 4(%0) \n" \
" stw 23, 8(%0) \n" \
" stw 24, 12(%0) \n" \
" stw 25, 16(%0) \n" \
" stw 26, 20(%0) \n" \
" stw 27, 24(%0) \n" \
" stw 29, 32(%0) \n" \
" stw 30, 36(%0) \n" \
" stw 31, 40(%0) \n" \
::"b"(addr))
#define SAVE_REG_28(addr) \
asm volatile( \
" stw 28, 28(%0) \n" \
::"b"(addr))
#define RESTORE_REGS(addr) \
asm volatile( \
" lwz 21, 0(%0) \n" \
" lwz 22, 4(%0) \n" \
" lwz 23, 8(%0) \n" \
" lwz 24, 12(%0) \n" \
" lwz 25, 16(%0) \n" \
" lwz 26, 20(%0) \n" \
" lwz 27, 24(%0) \n" \
" lwz 29, 32(%0) \n" \
" lwz 30, 36(%0) \n" \
" lwz 31, 400(%0) \n" \
::"b"(addr))
#define RESTORE_REG_28(addr) \
asm volatile( \
" lwz 28, 28(%0) \n" \
::"b"(addr))
#endif /* __powerpc64__ */
#define NUM_ENTRIES_SAVE_RESTORE 11
HWord_t temp[NUM_ENTRIES_SAVE_RESTORE];
static void test_pstxvp_off0_R1 (void) {
__asm__ __volatile__ ("pstxvp 20, -0x1f400+0(0),1");
@ -151,78 +62,54 @@ static void test_pstxvp_off48_R1 (void) {
__asm__ __volatile__ ("pstxvp 20, -0x1f400+48(0),1");
}
static void test_plfd_64_R1 (void) {
SAVE_REGS(temp);
__asm__ __volatile__ ("plfd 28, +64(0), 1");
PAD_ORI
PAD_ORI
RESTORE_REGS(temp);
}
static void test_plfd_32_R1 (void) {
SAVE_REGS(temp);
__asm__ __volatile__ ("plfd 28, +32(0), 1");
PAD_ORI
RESTORE_REGS(temp);
}
static void test_plfd_16_R1 (void) {
SAVE_REGS(temp);
__asm__ __volatile__ ("plfd 28, +16(0), 1");
PAD_ORI
RESTORE_REGS(temp);
}
static void test_plfd_8_R1 (void) {
SAVE_REGS(temp);
__asm__ __volatile__ ("plfd 28, +8(0), 1");
PAD_ORI
RESTORE_REGS(temp);
}
static void test_plfd_4_R1 (void) {
SAVE_REGS(temp);
__asm__ __volatile__ ("plfd 28, +4(0), 1");
PAD_ORI
RESTORE_REGS(temp);
}
static void test_plfd_0_R1 (void) {
SAVE_REGS(temp);
__asm__ __volatile__ ("plfd 28, +0(0), 1");
PAD_ORI
RESTORE_REGS(temp);
}
static void test_plfs_64_R1 (void) {
SAVE_REGS(temp);
__asm__ __volatile__ ("plfs 28, +64(0), 1");
PAD_ORI
PAD_ORI
RESTORE_REGS(temp);
}
static void test_plfs_32_R1 (void) {
SAVE_REGS(temp);
__asm__ __volatile__ ("plfs 28, +32(0), 1");
PAD_ORI
RESTORE_REGS(temp);
}
static void test_plfs_16_R1 (void) {
SAVE_REGS(temp);
__asm__ __volatile__ ("plfs 28, +16(0), 1");
PAD_ORI
RESTORE_REGS(temp);
}
static void test_plfs_8_R1 (void) {
SAVE_REGS(temp);
__asm__ __volatile__ ("plfs 28, +8(0), 1");
PAD_ORI
RESTORE_REGS(temp);
}
static void test_plfs_4_R1 (void) {
SAVE_REGS(temp);
__asm__ __volatile__ ("plfs 28, +4(0), 1");
PAD_ORI
RESTORE_REGS(temp);
}
static void test_plfs_0_R1 (void) {
SAVE_REGS(temp);
__asm__ __volatile__ ("plfs 28, +0(0), 1");
PAD_ORI
RESTORE_REGS(temp);
}
static void test_pstfd_32_R1 (void) {
__asm__ __volatile__ ("pstfd 26, -0x1f400+32(0), 1");
@ -255,102 +142,54 @@ static void test_pstfs_0_R1 (void) {
__asm__ __volatile__ ("pstfs 26, -0x1f400+0(0), 1");
}
static void test_plxsd_64_R1 (void) {
SAVE_REGS(temp);
SAVE_REG_28(temp);
__asm__ __volatile__ ("plxsd %0, +64(0), 1" : "=v" (vrt) );
PAD_ORI
PAD_ORI
RESTORE_REGS(temp);
RESTORE_REG_28(temp);
}
static void test_plxsd_32_R1 (void) {
SAVE_REGS(temp);
SAVE_REG_28(temp);
__asm__ __volatile__ (".align 2 ; plxsd %0, +32(0), 1" : "=v" (vrt) );
PAD_ORI
RESTORE_REGS(temp);
RESTORE_REG_28(temp);
}
static void test_plxsd_16_R1 (void) {
SAVE_REGS(temp);
SAVE_REG_28(temp);
__asm__ __volatile__ ("plxsd %0, +16(0), 1; pnop;pnop;pnop; " : "=v" (vrt) );
PAD_ORI
RESTORE_REGS(temp);
RESTORE_REG_28(temp);
}
static void test_plxsd_8_R1 (void) {
SAVE_REGS(temp);
SAVE_REG_28(temp);
__asm__ __volatile__ ("plxsd %0, +8(0), 1; pnop;pnop;pnop; " : "=v" (vrt) );
PAD_ORI
RESTORE_REGS(temp);
RESTORE_REG_28(temp);
}
static void test_plxsd_4_R1 (void) {
SAVE_REGS(temp);
SAVE_REG_28(temp);
__asm__ __volatile__ ("plxsd %0, +4(0), 1; pnop;pnop;pnop; " : "=v" (vrt) );
PAD_ORI
RESTORE_REGS(temp);
RESTORE_REG_28(temp);
}
static void test_plxsd_0_R1 (void) {
SAVE_REGS(temp);
SAVE_REG_28(temp);
__asm__ __volatile__ ("plxsd %0, +0(0), 1; pnop;pnop;pnop; " : "=v" (vrt) );
PAD_ORI
RESTORE_REGS(temp);
RESTORE_REG_28(temp);
}
static void test_plxssp_64_R1 (void) {
SAVE_REGS(temp);
SAVE_REG_28(temp);
__asm__ __volatile__ ("plxssp %0, +64(0), 1; pnop;pnop;pnop; " : "=v" (vrt) );
PAD_ORI
PAD_ORI
RESTORE_REGS(temp);
RESTORE_REG_28(temp);
}
static void test_plxssp_32_R1 (void) {
SAVE_REGS(temp);
SAVE_REG_28(temp);
__asm__ __volatile__ ("plxssp %0, +32(0), 1; pnop; " : "=v" (vrt) );
PAD_ORI
RESTORE_REGS(temp);
RESTORE_REG_28(temp);
}
static void test_plxssp_16_R1 (void) {
SAVE_REGS(temp);
SAVE_REG_28(temp);
__asm__ __volatile__ ("plxssp %0, +16(0), 1; pnop;pnop;pnop; " : "=v" (vrt) );
PAD_ORI
RESTORE_REGS(temp);
RESTORE_REG_28(temp);
}
static void test_plxssp_8_R1 (void) {
SAVE_REGS(temp);
SAVE_REG_28(temp);
__asm__ __volatile__ ("plxssp %0, +8(0), 1; pnop;pnop;pnop; " : "=v" (vrt) );
PAD_ORI
RESTORE_REGS(temp);
RESTORE_REG_28(temp);
}
static void test_plxssp_4_R1 (void) {
SAVE_REGS(temp);
SAVE_REG_28(temp);
__asm__ __volatile__ ("plxssp %0, +4(0), 1; pnop;pnop;pnop; " : "=v" (vrt) );
PAD_ORI
RESTORE_REGS(temp);
RESTORE_REG_28(temp);
}
static void test_plxssp_0_R1 (void) {
SAVE_REGS(temp);
SAVE_REG_28(temp);
__asm__ __volatile__ ("plxssp %0, +0(0), 1; pnop;pnop;pnop; " : "=v" (vrt) );
PAD_ORI
RESTORE_REGS(temp);
RESTORE_REG_28(temp);
}
/* Follow the short-range plxv instructions with nop in order to
pad out subsequent instructions. When written there are found
@ -358,36 +197,20 @@ static void test_plxssp_0_R1 (void) {
into the target variable. (pla,pstxv...).
*/
static void test_plxv_16_R1 (void) {
SAVE_REGS(temp);
SAVE_REG_28(temp);
__asm__ __volatile__ ("plxv %x0, +16(0), 1; pnop;pnop;pnop;" : "=wa" (vec_xt) );
PAD_ORI
RESTORE_REGS(temp);
RESTORE_REG_28(temp);
}
static void test_plxv_8_R1 (void) {
SAVE_REGS(temp);
SAVE_REG_28(temp);
__asm__ __volatile__ ("plxv %x0, +8(0), 1; pnop;pnop;pnop;" : "=wa" (vec_xt) );
PAD_ORI
RESTORE_REGS(temp);
RESTORE_REG_28(temp);
}
static void test_plxv_4_R1 (void) {
SAVE_REGS(temp);
SAVE_REG_28(temp);
__asm__ __volatile__ ("plxv %x0, +4(0), 1; pnop;pnop;pnop;" : "=wa" (vec_xt) );
PAD_ORI
RESTORE_REGS(temp);
RESTORE_REG_28(temp);
}
static void test_plxv_0_R1 (void) {
SAVE_REGS(temp);
SAVE_REG_28(temp);
__asm__ __volatile__ ("plxv %x0, +0(0), 1; pnop;pnop;pnop; " : "=wa" (vec_xt) );
PAD_ORI
RESTORE_REGS(temp);
RESTORE_REG_28(temp);
}
static void test_pstxsd_64_R1 (void) {
__asm__ __volatile__ (".align 2 ; pstxsd 22, -0x1f400+64(0), 1" );

28
none/tests/ppc64/test_isa_3_1_R1_XT.stdout.exp
View File

@ -28,7 +28,7 @@ plxsd 4_R1 => 7000000a8000004,0000000000000000 5.77662562e-275 +Zer
plxsd 8_R1 => 7000000,0000000000000000 +Den +Zero
plxsd 16_R1 => 700000060000000,0000000000000000 5.77662407e-275 +Zero
plxsd 16_R1 => 7000000,0000000000000000 +Den +Zero
plxsd 32_R1 => 6339001963180018,0000000000000000 9.43505226e+169 +Zero
@ -38,21 +38,21 @@ plxssp 0_R1 => 3882000000000000,0000000000000000 6.19888e-05 +Zero
plxssp 4_R1 => bd80000080000000,0000000000000000 -6.25000e-02 -Zero +Zero +Zero
plxssp 8_R1 => 4400000000000000,0000000000000000 5.12000e+02 +Zero +Zero +Zero
plxssp 8_R1 => 38e0000000000000,0000000000000000 1.06812e-04 +Zero +Zero +Zero
plxssp 16_R1 => 38e0000000000000,0000000000000000 1.06812e-04 +Zero +Zero +Zero
plxssp 32_R1 => 445ac002c0000000,0000000000000000 8.75000e+02 -2.00000e+00 +Zero +Zero
plxssp 64_R1 => 4467200320000000,0000000000000000 9.24500e+02 1.08420e-19 +Zero +Zero
plxssp 64_R1 => 446b400340000000,0000000000000000 9.41000e+02 2.00000e+00 +Zero +Zero
plxv 0_R1 => c800000004100000 700000060000000
plxv 0_R1 => c800000004100000 7000000
plxv 4_R1 => 60000000c8000004 7000000
plxv 4_R1 => 7000000c8000004 6000000000000000
plxv 8_R1 => 700000060000000 700000000000000
plxv 8_R1 => 7000000 7000000
plxv 16_R1 => 700000000000000 700000000000000
plxv 16_R1 => 7000000 7000000
pstfd 0_R1 43dfe000003fe000 43eff000000ff000 => e000003fe00043df
pstfd 0_R1 43eff000000ff000 43efefffffcff000 => f000000ff00043ef
@ -86,15 +86,15 @@ pstfs 32_R1 000000005f7f8000 000000005f7f8000 => 80005f7f
pstxsd 0_R1 => 0000000000000000
pstxsd 4_R1 => 00000000 00000000
pstxsd 4_R1 => 0000000000000000
pstxsd 8_R1 => 0000000000000000
pstxsd 8_R1 => 00000000 00000000
pstxsd 16_R1 => 0000000000000000
pstxsd 16_R1 => 00000000 00000000
pstxsd 32_R1 => 0000000000000000
pstxsd 32_R1 => 00000000 00000000
pstxsd 64_R1 => 0000000000000000
pstxsd 64_R1 => 00000000 00000000
pstxssp 0_R1 => 00000000
@ -116,9 +116,9 @@ pstxvp off32_R1 0180055e0180077e 0080000e8080000e ff7ffffe7f7ffffe ff8000007f800
pstxvp off48_R1 0180055e0180077e 0080000e8080000e ff7ffffe7f7ffffe ff8000007f800000 => fffe7f7ffffeff7f 00007f800000ff80 077e0180055e0180 000e8080000e0080
pstxv 0_R1 ff7ffffe7f7ffffe,ff8000007f800000 => fffe7f7ffffeff7f 00007f800000ff80
pstxv 0_R1 ff7ffffe7f7ffffe,ff8000007f800000 => fffe7f7f fffeff7f00007f80 0000ff80
pstxv 4_R1 ff7ffffe7f7ffffe,ff8000007f800000 => fffe7f7ffffeff7f 00007f800000ff80
pstxv 4_R1 ff7ffffe7f7ffffe,ff8000007f800000 => fffe7f7f fffeff7f00007f80 0000ff80
pstxv 8_R1 ff7ffffe7f7ffffe,ff8000007f800000 => fffe7f7ffffeff7f 00007f800000ff80