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https://github.com/Zenithsiz/ftmemsim-valgrind.git
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Change the core-tool interface so that tools are fully aware of both
the guest extents for the presented translation and also its original un-redirected guest address. These changes are needed in particular to make cachegrind's code cache management work properly. git-svn-id: svn://svn.valgrind.org/valgrind/trunk@4943
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@ -141,7 +141,7 @@ struct _InstrInfo {
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typedef struct _BB_info BB_info;
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struct _BB_info {
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Addr BB_addr; // key
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Addr BB_addr; // key; MUST BE FIRST
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Int n_instrs;
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InstrInfo instrs[0];
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};
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@ -452,6 +452,8 @@ typedef
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/*--- Instrumentation main ---*/
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/*------------------------------------------------------------*/
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// Note that origAddr is the real origAddr, not the address of the first
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// instruction in the block (they can be different due to redirection).
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static
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BB_info* get_BB_info(IRBB* bbIn, Addr origAddr)
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{
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@ -731,8 +733,10 @@ void addEvent_Dw ( CgState* cgs, InstrInfo* inode, Int datasize, IRAtom* ea )
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////////////////////////////////////////////////////////////
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static IRBB* cg_instrument ( IRBB* bbIn, VexGuestLayout* layout,
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IRType gWordTy, IRType hWordTy )
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static
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IRBB* cg_instrument ( IRBB* bbIn, VexGuestLayout* layout,
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Addr64 orig_addr_noredir, VexGuestExtents* vge,
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IRType gWordTy, IRType hWordTy )
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{
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Int i, isize;
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IRStmt* st;
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@ -763,7 +767,7 @@ static IRBB* cg_instrument ( IRBB* bbIn, VexGuestLayout* layout,
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// Set up running state and get block info
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cgs.events_used = 0;
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cgs.bbInfo = get_BB_info(bbIn, (Addr)cia);
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cgs.bbInfo = get_BB_info(bbIn, (Addr)orig_addr_noredir);
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cgs.bbInfo_i = 0;
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if (DEBUG_CG)
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@ -1241,18 +1245,22 @@ static void cg_fini(Int exitcode)
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// Called when a translation is removed from the translation cache for
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// any reason at all: to free up space, because the guest code was
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// unmapped or modified, or for any arbitrary reason.
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static void cg_discard_basic_block_info ( VexGuestExtents vge )
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static
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void cg_discard_basic_block_info ( Addr64 orig_addr64, VexGuestExtents vge )
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{
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BB_info* bbInfo;
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Addr orig_addr = (Addr)orig_addr64;
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tl_assert(vge.n_used > 0);
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if (DEBUG_CG)
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VG_(printf)( "discard_basic_block_info: %p, %llu\n",
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VG_(printf)( "discard_basic_block_info: %p, %p, %llu\n",
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(void*)(Addr)orig_addr,
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(void*)(Addr)vge.base[0], (ULong)vge.len[0]);
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// Get BB info, remove from table, free BB info. Simple!
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bbInfo = VG_(OSet_Remove)(instrInfoTable, &(vge.base[0]));
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// Get BB info, remove from table, free BB info. Simple! Note that we
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// use orig_addr, not the first instruction address in vge.
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bbInfo = VG_(OSet_Remove)(instrInfoTable, &orig_addr);
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tl_assert(NULL != bbInfo);
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VG_(OSet_FreeNode)(instrInfoTable, bbInfo);
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}
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@ -1375,7 +1383,7 @@ static void cg_pre_clo_init(void)
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CC_table = VG_(OSet_Create)(offsetof(LineCC, loc),
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cmp_CodeLoc_LineCC,
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VG_(malloc), VG_(free));
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instrInfoTable = VG_(OSet_Create)(offsetof(BB_info, BB_addr),
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instrInfoTable = VG_(OSet_Create)(/*keyOff*/0,
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NULL,
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VG_(malloc), VG_(free));
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stringTable = VG_(OSet_Create)(/*keyOff*/0,
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@ -40,7 +40,8 @@ VgToolInterface VG_(tdict);
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void VG_(basic_tool_funcs)(
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void(*post_clo_init)(void),
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IRBB*(*instrument)(IRBB*, VexGuestLayout*, IRType, IRType ),
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IRBB*(*instrument)(IRBB*, VexGuestLayout*,
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Addr64, VexGuestExtents*, IRType, IRType ),
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void(*fini)(Int)
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)
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{
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@ -154,7 +155,7 @@ NEEDS(core_errors)
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NEEDS(data_syms)
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void VG_(needs_basic_block_discards)(
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void (*discard)(VexGuestExtents)
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void (*discard)(Addr64, VexGuestExtents)
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)
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{
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VG_(needs).basic_block_discards = True;
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@ -166,8 +166,12 @@ static Bool need_to_handle_SP_assignment(void)
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*/
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static
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IRBB* vg_SP_update_pass ( IRBB* bb_in, VexGuestLayout* layout,
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IRType gWordTy, IRType hWordTy )
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IRBB* vg_SP_update_pass ( IRBB* bb_in,
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VexGuestLayout* layout,
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Addr64 orig_addr_noredir,
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VexGuestExtents* vge,
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IRType gWordTy,
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IRType hWordTy )
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{
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Int i, j, minoff_ST, maxoff_ST, sizeof_SP, offset_SP;
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IRDirty *dcall, *d;
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@ -520,7 +524,7 @@ Bool VG_(translate) ( ThreadId tid,
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Int debugging_verbosity,
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ULong bbs_done )
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{
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Addr64 redir, orig_addr0 = orig_addr;
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Addr64 redir, orig_addr_noredir = orig_addr;
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Int tmpbuf_used, verbosity, i;
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Bool notrace_until_done, do_self_check;
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UInt notrace_until_limit = 0;
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@ -672,6 +676,7 @@ Bool VG_(translate) ( ThreadId tid,
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vex_arch, &vex_archinfo,
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(UChar*)ULong_to_Ptr(orig_addr),
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(Addr64)orig_addr,
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(Addr64)orig_addr_noredir,
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chase_into_ok,
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&vge,
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tmpbuf, N_TMPBUF, &tmpbuf_used,
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@ -711,10 +716,10 @@ Bool VG_(translate) ( ThreadId tid,
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// If debugging, don't do anything with the translated block; we
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// only did this for the debugging output produced along the way.
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if (!debugging_translation) {
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// Note that we use orig_addr0, not orig_addr, which might have been
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// changed by the redirection
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// Note that we use orig_addr_noredir, not orig_addr, which
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// might have been changed by the redirection
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VG_(add_to_transtab)( &vge,
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orig_addr0,
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orig_addr_noredir,
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(Addr)(&tmpbuf[0]),
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tmpbuf_used,
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do_self_check );
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@ -688,6 +688,7 @@ static void initialiseSector ( Int sno )
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/* Tell the tool too. */
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if (VG_(needs).basic_block_discards) {
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VG_TDICT_CALL( tool_discard_basic_block_info,
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sec->tt[i].entry,
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sec->tt[i].vge );
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}
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} else {
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@ -1011,6 +1012,7 @@ static void delete_tte ( /*MOD*/Sector* sec, Int tteno )
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/* Tell the tool too. */
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if (VG_(needs).basic_block_discards) {
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VG_TDICT_CALL( tool_discard_basic_block_info,
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tte->entry,
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tte->vge );
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}
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}
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@ -104,7 +104,8 @@ typedef struct {
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// Basic functions
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void (*tool_pre_clo_init) (void);
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void (*tool_post_clo_init)(void);
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IRBB* (*tool_instrument) (IRBB*, VexGuestLayout*, IRType, IRType);
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IRBB* (*tool_instrument) (IRBB*, VexGuestLayout*,
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Addr64, VexGuestExtents*, IRType, IRType);
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void (*tool_fini) (Int);
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// VG_(needs).core_errors
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@ -121,7 +122,7 @@ typedef struct {
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void (*tool_print_extra_suppression_info)(Error*);
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// VG_(needs).basic_block_discards
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void (*tool_discard_basic_block_info)(VexGuestExtents);
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void (*tool_discard_basic_block_info)(Addr64, VexGuestExtents);
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// VG_(needs).command_line_options
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Bool (*tool_process_cmd_line_option)(Char*);
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@ -2297,8 +2297,10 @@ UCodeBlock* TL_(instrument) ( UCodeBlock* cb_in, Addr not_used )
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return cb;
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}
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#endif
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static IRBB* hg_instrument ( IRBB* bb_in, VexGuestLayout* layout,
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IRType gWordTy, IRType hWordTy )
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static
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IRBB* hg_instrument ( IRBB* bb_in, VexGuestLayout* layout,
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Addr64 orig_addr_noredir, VexGuestExtents* vge,
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IRType gWordTy, IRType hWordTy )
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{
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tl_assert(0); // Need to convert to Vex
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}
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@ -78,10 +78,14 @@ extern void VG_(basic_tool_funcs)(
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// processing.
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void (*post_clo_init)(void),
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// Instrument a basic block. Must be a true function, ie. the same input
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// always results in the same output, because basic blocks can be
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// retranslated. Unless you're doing something really strange...
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IRBB* (*instrument)(IRBB* bb_in, VexGuestLayout* layout,
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// Instrument a basic block. Must be a true function, ie. the same
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// input always results in the same output, because basic blocks
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// can be retranslated. Unless you're doing something really
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// strange... Note that orig_addr_noredir is not necessarily the
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// same as the address of the first instruction in the IR, due to
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// function redirection.
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IRBB* (*instrument)(IRBB* bb_in, VexGuestLayout* layout,
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Addr64 orig_addr_noredir, VexGuestExtents* vge,
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IRType gWordTy, IRType hWordTy ),
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// Finish up, print out any results, etc. `exitcode' is program's exit
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@ -195,19 +199,21 @@ extern void VG_(needs_tool_errors) (
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reused for new translations. */
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extern void VG_(needs_basic_block_discards) (
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// Discard any information that pertains to specific translations
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// or instructions within the address range given. The "extents"
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// arg can be used in two ways.
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// - If info is being stored at a per-translation level, the first
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// address in the extents can be used to identify which translation
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// is being discarded. Each translation will be discarded exactly
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// once.
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// or instructions within the address range given. There are two
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// possible approaches.
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// - If info is being stored at a per-translation level, use orig_addr
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// to identify which translation is being discarded. Each translation
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// will be discarded exactly once.
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// This orig_addr will match the orig_addr which was passed to
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// to instrument() when this translation was made. Note that orig_addr
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// won't necessarily be the same as the first address in "extents".
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// - If info is being stored at a per-instruction level, you can get
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// the address range(s) being discarded by stepping through "extents".
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// Note that any single instruction may belong to more than one
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// translation, and so could be covered by the "extents" of more than
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// one call to this function.
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// Doing it the first way (as eg. Cachegrind does) is probably easier.
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void (*discard_basic_block_info)(VexGuestExtents vge)
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void (*discard_basic_block_info)(Addr64 orig_addr, VexGuestExtents extents)
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);
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/* Tool defines its own command line options? */
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@ -124,8 +124,10 @@ static void lk_post_clo_init(void)
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Which gives us the right answer. And just to avoid two C calls, we fold
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the basic-block-beginning call in with add_one_BB(). Phew.
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*/
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static IRBB* lk_instrument(IRBB* bb_in, VexGuestLayout* layout,
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IRType gWordTy, IRType hWordTy )
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static
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IRBB* lk_instrument( IRBB* bb_in, VexGuestLayout* layout,
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Addr64 orig_addr_noredir, VexGuestExtents* vge,
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IRType gWordTy, IRType hWordTy )
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{
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IRDirty* di;
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Int i;
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@ -1148,8 +1148,10 @@ static Bool ms_handle_client_request ( ThreadId tid, UWord* argv, UWord* ret )
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/*--- Instrumentation ---*/
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/*------------------------------------------------------------*/
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static IRBB* ms_instrument ( IRBB* bb_in, VexGuestLayout* layout,
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IRType gWordTy, IRType hWordTy )
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static
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IRBB* ms_instrument ( IRBB* bb_in, VexGuestLayout* layout,
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Addr64 orig_addr_noredir, VexGuestExtents* vge,
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IRType gWordTy, IRType hWordTy )
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{
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/* XXX Will Massif work when gWordTy != hWordTy ? */
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return bb_in;
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@ -79,9 +79,10 @@ extern VG_REGPARM(1) UWord MC_(helperc_LOADV1) ( Addr );
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extern void MC_(helperc_MAKE_STACK_UNINIT) ( Addr base, UWord len );
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/* Functions defined in mc_translate.c */
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extern IRBB* MC_(instrument) ( IRBB* bb_in, VexGuestLayout* layout,
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IRType gWordTy, IRType hWordTy );
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extern
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IRBB* MC_(instrument) ( IRBB* bb_in, VexGuestLayout* layout,
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Addr64 orig_addr_noredir, VexGuestExtents* vge,
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IRType gWordTy, IRType hWordTy );
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#endif /* ndef __MC_INCLUDE_H */
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@ -2810,6 +2810,7 @@ static Bool checkForBogusLiterals ( /*FLAT*/ IRStmt* st )
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IRBB* MC_(instrument) ( IRBB* bb_in, VexGuestLayout* layout,
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Addr64 orig_addr_noredir, VexGuestExtents* vge,
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IRType gWordTy, IRType hWordTy )
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{
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Bool verboze = False; //True;
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@ -36,8 +36,10 @@ static void nl_post_clo_init(void)
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{
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}
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static IRBB* nl_instrument(IRBB* bb, VexGuestLayout* layout,
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IRType gWordTy, IRType hWordTy)
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static
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IRBB* nl_instrument(IRBB* bb, VexGuestLayout* layout,
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Addr64 orig_addr_noredir, VexGuestExtents* vge,
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IRType gWordTy, IRType hWordTy)
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{
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return bb;
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}
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