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https://github.com/Zenithsiz/ftmemsim-valgrind.git
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s390: Add testcase for the ecag insn. Based on patch by
Divya Vyas (divyvyas@linux.vnet.ibm.com). Update opcode list. git-svn-id: svn://svn.valgrind.org/valgrind/trunk@12903
This commit is contained in:
Florian Krohm
parent
7bea862277
commit
16690f1ef5
1
NEWS
1
NEWS
@ -22,6 +22,7 @@ where XXXXXX is the bug number as listed below.
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219156 [380] handle statically linked malloc and/or other malloc libs
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254088 [380] Valgrind should know about UD2 instruction
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275800 [380] s390x: Add support for the ecag instruction (part 1)
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284004 [381] == 301281
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289584 [381] Unhandled instruction: 0xF 0x29 0xE5 (MOVAPS)
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295808 [381] amd64->IR: 0xF3 0xF 0xBC 0xC0 (TZCNT)
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@ -790,7 +790,7 @@ clrt,"compare logical and trap (32)","not implemented",
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clgrt,"compare logical and trap (64)","not implemented",
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clfit,"compare logical and trap (32<16)","not implemented",
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clgit,"compare logical and trap (64<16)","not implemented",
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ecag,"extract cache attribute","not implemented","open bugzilla"
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ecag,"extract cache attribute",implemented,
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lrl,"load relative long (32)",implemented,
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lgrl,"load relative long (64)",implemented,
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lgfrl,"load relative long (64<32)",implemented,
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Can't render this file because it has a wrong number of fields in line 662.
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@ -8,7 +8,7 @@ INSN_TESTS = clc clcle cvb cvd icm lpr tcxb lam_stam xc mvst add sub mul \
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op_exception fgx stck stckf stcke stfle cksm mvcl clcl troo \
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trto trot trtt tr tre cij cgij clij clgij crj cgrj clrj clgrj \
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cs csg cds cdsg cu21 cu21_1 cu24 cu24_1 cu42 cu12 cu12_1 \
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ex_sig ex_clone cu14 cu14_1 cu41 fpconv
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ex_sig ex_clone cu14 cu14_1 cu41 fpconv ecag
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check_PROGRAMS = $(INSN_TESTS) \
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allexec \
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73
none/tests/s390x/ecag.c
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73
none/tests/s390x/ecag.c
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@ -0,0 +1,73 @@
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#include <stdio.h>
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#include <assert.h>
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#include <stdint.h>
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#include <inttypes.h>
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#include "opcodes.h"
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uint64_t
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ecag(int ai, int li, int ti)
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{
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register uint64_t result asm("2") = 0;
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register uint64_t input asm("3") = (ai << 4) | (li << 1) | ti;
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asm volatile( ECAG(2,0,3,000,00)
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: "=d" (result) : "d" (input));
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return result;
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}
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static unsigned
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get_level_info(uint64_t topology, unsigned level)
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{
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return (topology >> (56 - level * 8)) & 0xff;
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}
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int
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main(void)
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{
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unsigned level;
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uint64_t topology;
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topology = ecag(0, 0, 0); // get summary
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/* ECAG supports at most 8 levels of cache. Iterate over all of them
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ignoring those not present. */
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for (level = 0; level < 8; level++) {
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unsigned info = get_level_info(topology, level);
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if ((info & 0xc) == 0) continue; // cache does not exist at this level
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unsigned cache_type = info & 0x3;
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unsigned cache_scope = (info & 0xc) >> 2;
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char *type, *scope;
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switch (cache_type) {
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case 0: type = "separate data and instruction"; break;
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case 1: type = "instruction"; break;
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case 2: type = "data"; break;
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case 3: type = "unified data and instruction"; break;
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}
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switch (cache_scope) {
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case 0: assert(0); // should never occur because cache exists
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case 1: scope = "private"; break;
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case 2: scope = "shared"; break;
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case 3: scope = "reserved"; break;
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}
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printf("L%u topology: %s; %s\n", level+1, type, scope);
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printf("L%u cache line size data: %"PRId64"\n", level+1,
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ecag(1, level, 0));
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printf("L%u cache line size insn: %"PRId64"\n", level+1,
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ecag(1, level, 1));
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printf("L%u total cachesize data: %"PRId64"\n", level+1,
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ecag(2, level, 0));
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printf("L%u total cachesize insn: %"PRId64"\n", level+1,
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ecag(2, level, 1));
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printf("L%u set. assoc. data: %"PRId64"\n", level+1,
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ecag(3, level, 0));
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printf("L%u set. assoc. insn: %"PRId64"\n", level+1,
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ecag(3, level, 1));
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}
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return 0;
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}
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2
none/tests/s390x/ecag.stderr.exp
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2
none/tests/s390x/ecag.stderr.exp
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@ -0,0 +1,2 @@
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21
none/tests/s390x/ecag.stdout.exp-z10ec
Normal file
21
none/tests/s390x/ecag.stdout.exp-z10ec
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L1 topology: separate data and instruction; private
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L1 cache line size data: 256
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L1 cache line size insn: 256
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L1 total cachesize data: 131072
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L1 total cachesize insn: 65536
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L1 set. assoc. data: 8
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L1 set. assoc. insn: 4
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L2 topology: unified data and instruction; private
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L2 cache line size data: 256
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L2 cache line size insn: 256
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L2 total cachesize data: 3145728
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L2 total cachesize insn: 3145728
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L2 set. assoc. data: 12
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L2 set. assoc. insn: 12
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L3 topology: unified data and instruction; shared
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L3 cache line size data: 256
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L3 cache line size insn: 256
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L3 total cachesize data: 50331648
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L3 total cachesize insn: 50331648
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L3 set. assoc. data: 24
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L3 set. assoc. insn: 24
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28
none/tests/s390x/ecag.stdout.exp-z196
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28
none/tests/s390x/ecag.stdout.exp-z196
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L1 topology: separate data and instruction; private
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L1 cache line size data: 256
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L1 cache line size insn: 256
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L1 total cachesize data: 131072
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L1 total cachesize insn: 65536
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L1 set. assoc. data: 8
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L1 set. assoc. insn: 4
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L2 topology: unified data and instruction; private
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L2 cache line size data: 256
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L2 cache line size insn: 256
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L2 total cachesize data: 1572864
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L2 total cachesize insn: 1572864
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L2 set. assoc. data: 12
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L2 set. assoc. insn: 12
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L3 topology: unified data and instruction; shared
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L3 cache line size data: 256
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L3 cache line size insn: 256
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L3 total cachesize data: 25165824
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L3 total cachesize insn: 25165824
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L3 set. assoc. data: 12
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L3 set. assoc. insn: 12
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L4 topology: unified data and instruction; shared
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L4 cache line size data: 256
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L4 cache line size insn: 256
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L4 total cachesize data: 201326592
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L4 total cachesize insn: 201326592
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L4 set. assoc. data: 24
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L4 set. assoc. insn: 24
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2
none/tests/s390x/ecag.vgtest
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2
none/tests/s390x/ecag.vgtest
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@ -0,0 +1,2 @@
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prereq: ../../../tests/s390x_features s390x-genins
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prog: ecag
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@ -277,6 +277,7 @@
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#define SHHLR(r3,r1,r2) RRF_R0RR2(b9d9,r3,0,r1,r2)
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#define SHY(r1,x2,b2,dl2,dh2) RXY_RRRD(e3,r1,x2,b2,dl2,dh2,7b)
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#define SLAK(r1,r3,b2,dl2,dh2) RSY_RRRD(eb,r1,r3,b2,dl2,dh2,dd)
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#define ECAG(r1,r3,b2,dl2,dh2) RSY_RRRD(eb,r1,r3,b2,dl2,dh2,4c)
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#define SLFI(r1,i2) RIL_RU(c2,r1,5,i2)
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#define SLGFI(r1,i2) RIL_RU(c2,r1,4,i2)
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#define SLGRK(r3,r1,r2) RRF_R0RR2(b9eb,r3,0,r1,r2)
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