mirror of
https://github.com/Zenithsiz/ftmemsim-valgrind.git
synced 2026-02-04 02:18:37 +00:00
Implement enough SSE/SSE2 insns so that all the GL demos in qt-3.1.0
work, when running on a P4 with an NVidia Vanta card and using NVidia-supplied libGL.so.1.0.3123. Surprisingly this seems to require only a minimal set of instructions. So far this is only with --skin=none. git-svn-id: svn://svn.valgrind.org/valgrind/trunk@1652
This commit is contained in:
Julian Seward
parent
5777e313ad
commit
0facd982d2
@ -1499,6 +1499,22 @@ static void emit_SSE4 ( FlagSet uses_sflags,
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(UInt)third_byte, (UInt)fourth_byte );
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}
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static void emit_SSE3 ( FlagSet uses_sflags,
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FlagSet sets_sflags,
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UChar first_byte,
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UChar second_byte,
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UChar third_byte )
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{
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VG_(new_emit)(True, uses_sflags, sets_sflags);
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VG_(emitB) ( first_byte );
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VG_(emitB) ( second_byte );
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VG_(emitB) ( third_byte );
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if (dis)
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VG_(printf)("\n\t\tsse-0x%x:0x%x:0x%x\n",
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(UInt)first_byte, (UInt)second_byte,
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(UInt)third_byte );
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}
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static void emit_MMX2_reg_to_mmxreg ( FlagSet uses_sflags,
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FlagSet sets_sflags,
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UChar first_byte,
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@ -3745,6 +3761,22 @@ static void emitUInstr ( UCodeBlock* cb, Int i,
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u->val2 & 0xFF );
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break;
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case SSE3:
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vg_assert(u->size == 0);
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vg_assert(u->tag1 == Lit16);
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vg_assert(u->tag2 == Lit16);
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vg_assert(u->tag3 == NoValue);
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vg_assert(!anyFlagUse(u));
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if (!(*sselive)) {
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emit_get_sse_state();
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*sselive = True;
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}
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emit_SSE3 ( u->flags_r, u->flags_w,
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(u->val1 >> 8) & 0xFF,
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u->val1 & 0xFF,
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u->val2 & 0xFF );
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break;
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default:
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if (VG_(needs).extended_UCode) {
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if (*sselive) {
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@ -3282,8 +3282,9 @@ Addr dis_SSE3_reg_or_mem ( UCodeBlock* cb,
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Lit16, (((UShort)opc3) << 8) | (UShort)modrm );
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if (dis)
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VG_(printf)("%s %s, %s\n", name,
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nameXMMReg(eregOfRM(modrm)), nameXMMReg(gregOfRM(modrm)) );
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eip++;
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nameXMMReg(eregOfRM(modrm)),
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nameXMMReg(gregOfRM(modrm)) );
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eip++;
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} else {
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VG_(core_panic)("dis_SSE3_reg_or_mem: mem");
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}
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@ -3291,6 +3292,79 @@ Addr dis_SSE3_reg_or_mem ( UCodeBlock* cb,
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}
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/* Simple SSE operations, either
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op (src)xmmreg, (dst)xmmreg
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or
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op (src)address, (dst)xmmreg
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It is assumed that there are 2 opcode bytes preceding the start
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of the address mode. eip points to the first opcode byte.
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*/
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static
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Addr dis_SSE2_reg_or_mem ( UCodeBlock* cb,
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UChar sorb,
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Char* name,
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Int sz,
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Addr eip )
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{
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UChar opc1 = getUChar(eip);
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UChar opc2 = getUChar(eip+1);
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UChar modrm = getUChar(eip+2);
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eip += 2;
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if (epartIsReg(modrm)) {
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/* Completely internal SSE insn. */
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uInstr2(cb, SSE3, 0, /* ignore sz for internal ops */
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Lit16, (((UShort)opc1) << 8) | (UShort)opc2,
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Lit16, (UShort)modrm );
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if (dis)
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VG_(printf)("%s %s, %s\n", name,
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nameXMMReg(eregOfRM(modrm)),
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nameXMMReg(gregOfRM(modrm)) );
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eip++;
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} else {
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VG_(core_panic)("dis_SSE2_reg_or_mem: mem");
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}
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return eip;
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}
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/* Simple SSE operations, either
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op (src)xmmreg, (dst)xmmreg
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or
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op (src)address, (dst)xmmreg
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It is assumed that there are 2 opcode bytes preceding the start of
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the address mode. Also there is an 8-bit immediate following the
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address mode. eip points to the first opcode byte.
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*/
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static
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Addr dis_SSE2_reg_or_mem_Imm8 ( UCodeBlock* cb,
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UChar sorb,
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Char* name,
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Int sz,
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Addr eip )
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{
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UChar opc1 = getUChar(eip);
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UChar opc2 = getUChar(eip+1);
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UChar modrm = getUChar(eip+2);
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UChar imm8;
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eip += 2;
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if (epartIsReg(modrm)) {
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/* Completely internal SSE insn. */
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eip++;
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imm8 = getUChar(eip);
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uInstr2(cb, SSE4, 0, /* ignore sz for internal ops */
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Lit16, (((UShort)opc1) << 8) | (UShort)opc2,
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Lit16, (((UShort)modrm) << 8) | (UShort)imm8 );
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if (dis)
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VG_(printf)("%s %s, %s\n", name,
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nameXMMReg(eregOfRM(modrm)),
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nameXMMReg(gregOfRM(modrm)) );
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eip++;
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} else {
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VG_(core_panic)("dis_SSE2_reg_or_mem_Imm8: mem");
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}
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return eip;
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}
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/*------------------------------------------------------------*/
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/*--- Disassembling entire basic blocks ---*/
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@ -3308,6 +3382,10 @@ static Addr disInstr ( UCodeBlock* cb, Addr eip, Bool* isEnd )
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UChar dis_buf[50];
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Int am_sz, d_sz;
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/* Holds eip at the start of the insn, so that we can print
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consistent error messages for unimplemented insns. */
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UChar* eip_start = (UChar*)eip;
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/* sz denotes the nominal data-op size of the insn; we change it to
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2 if an 0x66 prefix is seen */
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Int sz = 4;
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@ -3393,10 +3471,11 @@ static Addr disInstr ( UCodeBlock* cb, Addr eip, Bool* isEnd )
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if (VG_(have_ssestate)) {
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UChar* insn = (UChar*)eip;
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/* STMXCSR/LDMXCSR m32 */
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/* STMXCSR/LDMXCSR m32 -- load/store the MXCSR register. */
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if (insn[0] == 0x0F && insn[1] == 0xAE
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&& (gregOfRM(insn[2]) == 3 || gregOfRM(insn[2]) == 2) ) {
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Bool store = gregOfRM(insn[2]) == 3;
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vg_assert(sz == 4);
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pair = disAMode ( cb, sorb, eip+2, dis?dis_buf:NULL );
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t1 = LOW24(pair);
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eip += 2+HI8(pair);
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@ -3406,11 +3485,12 @@ static Addr disInstr ( UCodeBlock* cb, Addr eip, Bool* isEnd )
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TempReg, t1 );
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if (dis)
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VG_(printf)("%smxcsr %s\n", store ? "st" : "ld", dis_buf );
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goto sse_done;
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goto decode_success;
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}
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/* CVTSI2SS */
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/* CVTSI2SS -- convert int reg to low 4 bytes of XMM reg. */
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if (insn[0] == 0xF3 && insn[1] == 0x0F && insn[2] == 0x2A) {
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vg_assert(sz == 4);
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modrm = insn[3];
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t1 = newTemp(cb);
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if (epartIsReg(modrm)) {
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@ -3436,17 +3516,41 @@ static Addr disInstr ( UCodeBlock* cb, Addr eip, Bool* isEnd )
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VG_(printf)("cvtsi2ss %s, %s\n", dis_buf,
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nameXMMReg(gregOfRM(modrm)));
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}
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goto sse_done;
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goto decode_success;
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}
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/* DIVSS */
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/* DIVSS -- divide low 4 bytes of XMM reg. */
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if (insn[0] == 0xF3 && insn[1] == 0x0F && insn[2] == 0x5E) {
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vg_assert(sz == 4);
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eip = dis_SSE3_reg_or_mem ( cb, sorb, "divss", 4, eip );
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goto sse_done;
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goto decode_success;
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}
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/* MOVSS */
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if (insn[0] == 0xF3 && insn[1] == 0x0F && insn[2] == 0x11) {
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/* SHUFPS */
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if (insn[0] == 0x0F && insn[1] == 0xC6) {
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vg_assert(sz == 4);
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eip = dis_SSE2_reg_or_mem_Imm8 ( cb, sorb, "shufps", 16, eip );
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goto decode_success;
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}
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/* MULPS */
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if (insn[0] == 0x0F && insn[1] == 0x59) {
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vg_assert(sz == 4);
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eip = dis_SSE2_reg_or_mem ( cb, sorb, "mulps", 16, eip );
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goto decode_success;
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}
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/* ADDPS */
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if (insn[0] == 0x0F && insn[1] == 0x58) {
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vg_assert(sz == 4);
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eip = dis_SSE2_reg_or_mem ( cb, sorb, "addps", 16, eip );
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goto decode_success;
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}
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/* MOVSS -- move 4 bytes of XMM reg to/from XMM reg or mem. */
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if (insn[0] == 0xF3 && insn[1] == 0x0F && (insn[2] == 0x11
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|| insn[2] == 0x10)) {
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vg_assert(sz == 4);
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if (epartIsReg(insn[3])) {
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/* MOVSS xmm, xmm */
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VG_(core_panic)("MOVSS reg");
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@ -3467,7 +3571,40 @@ static Addr disInstr ( UCodeBlock* cb, Addr eip, Bool* isEnd )
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VG_(printf)("movss %s, %s\n",
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dis_buf, nameXMMReg(gregOfRM(insn[3])) );
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}
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goto sse_done;
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goto decode_success;
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}
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/* MOVAPS (28,29) -- aligned load/store of XMM reg, or x-x reg move */
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/* MOVUPS (10,11) -- unaligned load/store of XMM reg, or x-x reg move */
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if (insn[0] == 0x0F && (insn[1] == 0x28
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|| insn[1] == 0x29
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|| insn[1] == 0x10
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|| insn[1] == 0x11)) {
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vg_assert(sz == 4);
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modrm = insn[2];
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if (epartIsReg(modrm)) {
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VG_(core_panic)("MOVAPS - reg");
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} else {
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Bool store = insn[1] == 0x29 || insn[1] == 11;
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pair = disAMode ( cb, sorb, eip+2, dis?dis_buf:NULL );
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t1 = LOW24(pair);
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eip += 2+HI8(pair);
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uInstr3(cb, store ? SSE2a_MemWr : SSE2a_MemRd, 16,
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Lit16, (((UShort)insn[0]) << 8) | (UShort)insn[1],
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Lit16, (UShort)insn[2],
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TempReg, t1 );
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if (dis) {
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UChar* name = (insn[1] == 0x10 || insn[1] == 0x11)
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? "movups" : "movaps";
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if (store)
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VG_(printf)("%s %s, %s\n",
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name, nameXMMReg(gregOfRM(modrm)), dis_buf );
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else
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VG_(printf)("%s %s, %s\n",
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name, dis_buf, nameXMMReg(gregOfRM(modrm)) );
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}
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}
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goto decode_success;
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}
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/* Fall through into the non-SSE decoder. */
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@ -4422,8 +4559,7 @@ static Addr disInstr ( UCodeBlock* cb, Addr eip, Bool* isEnd )
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if (dis) VG_(printf)("repne scas%c\n", nameISize(sz));
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}
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else {
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VG_(printf)("REPNE then 0x%x\n", (UInt)abyte);
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VG_(core_panic)("Unhandled REPNE case");
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goto decode_failure;
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}
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break;
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}
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@ -4459,9 +4595,7 @@ static Addr disInstr ( UCodeBlock* cb, Addr eip, Bool* isEnd )
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if (dis) VG_(printf)("repe nop (P4 pause)\n");
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/* do nothing; apparently a hint to the P4 re spin-wait loop */
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} else {
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VG_(printf)("Insn bytes: 0xF3 0x%x 0x%x\n",
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(UInt)abyte, (UInt)getUChar(eip));
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VG_(core_panic)("Unhandled REPE case");
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goto decode_failure;
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}
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break;
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}
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@ -4914,10 +5048,10 @@ static Addr disInstr ( UCodeBlock* cb, Addr eip, Bool* isEnd )
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vg_assert(sz == 4);
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modrm = getUChar(eip);
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if (epartIsReg(modrm)) {
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goto unimp2;
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goto decode_failure;
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}
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if (gregOfRM(modrm) > 3) {
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goto unimp2;
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goto decode_failure;
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}
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eip += lengthAMode(eip);
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if (dis) {
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@ -4927,7 +5061,7 @@ static Addr disInstr ( UCodeBlock* cb, Addr eip, Bool* isEnd )
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case 1: hintstr = "t0"; break;
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case 2: hintstr = "t1"; break;
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case 3: hintstr = "t2"; break;
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default: goto unimp2;
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default: goto decode_failure;
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}
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VG_(printf)("prefetch%s ...\n", hintstr);
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}
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@ -4948,7 +5082,7 @@ static Addr disInstr ( UCodeBlock* cb, Addr eip, Bool* isEnd )
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/* ok */
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} else {
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eip -= 2;
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goto unimp2;
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goto decode_failure;
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}
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uInstr2(cb, MMX3, 0,
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Lit16, (((UShort)byte1) << 8) | ((UShort)byte2),
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@ -5066,7 +5200,7 @@ static Addr disInstr ( UCodeBlock* cb, Addr eip, Bool* isEnd )
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vg_assert(sz == 4);
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modrm = getUChar(eip);
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if (epartIsReg(modrm)) {
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goto unimp2;
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goto decode_failure;
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} else {
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Int tmpa;
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pair = disAMode ( cb, sorb, eip, dis?dis_buf:NULL );
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@ -5214,42 +5348,41 @@ static Addr disInstr ( UCodeBlock* cb, Addr eip, Bool* isEnd )
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/* =-=-=-=-=-=-=-=-=- unimp2 =-=-=-=-=-=-=-=-=-=-= */
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default:
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unimp2:
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VG_(printf)("disInstr: unhandled 2-byte opcode: "
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"0x%x 0x%x 0x%x\n",
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(Int)getUChar(eip-1),
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(Int)getUChar(eip+0),
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(Int)getUChar(eip+1) );
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VG_(printf)("This _might_ be the result of executing a "
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"SSE, SSE2 or 3DNow!\n" );
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VG_(printf)("instruction. Valgrind does not currently "
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"support such instructions. Sorry.\n" );
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uInstr0(cb, CALLM_S, 0);
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uInstr1(cb, CALLM, 0, Lit16,
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VGOFF_(helper_undefined_instruction));
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uInstr0(cb, CALLM_E, 0);
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/* just because everything else insists the last instruction
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of a BB is a jmp */
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uInstr1(cb, JMP, 0, Literal, 0);
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uCond(cb, CondAlways);
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uLiteral(cb, eip);
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*isEnd = True;
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}
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break;
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}
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goto decode_failure;
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} /* switch (opc) for the 2-byte opcodes */
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goto decode_success;
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} /* case 0x0F: of primary opcode */
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/* ------------------------ ??? ------------------------ */
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default:
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decode_failure:
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/* All decode failures end up here. */
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VG_(printf)("disInstr: unhandled instruction bytes: "
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"0x%x 0x%x 0x%x 0x%x\n",
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(Int)eip_start[0],
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(Int)eip_start[1],
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(Int)eip_start[2],
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(Int)eip_start[3] );
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default:
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VG_(printf)("disInstr: unhandled opcode 0x%x then 0x%x\n",
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(UInt)opc, (UInt)getUChar(eip));
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VG_(core_panic)("unhandled x86 opcode");
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}
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uInstr0(cb, CALLM_S, 0);
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uInstr1(cb, CALLM, 0, Lit16,
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VGOFF_(helper_undefined_instruction));
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uInstr0(cb, CALLM_E, 0);
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|
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sse_done:
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/* just because everything else insists the last instruction of
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a BB is a jmp */
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uInstr1(cb, JMP, 0, Literal, 0);
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uCond(cb, CondAlways);
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uLiteral(cb, eip);
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*isEnd = True;
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break;
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return eip;
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|
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} /* switch (opc) for the main (primary) opcode switch. */
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|
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decode_success:
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/* All decode successes end up here. */
|
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if (dis)
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VG_(printf)("\n");
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for (; first_uinstr < cb->used; first_uinstr++) {
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@ -5260,7 +5393,6 @@ static Addr disInstr ( UCodeBlock* cb, Addr eip, Bool* isEnd )
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VG_(up_UInstr)(-1, &cb->instrs[first_uinstr]);
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vg_assert(sane);
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}
|
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|
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return eip;
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}
|
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|
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|
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@ -562,6 +562,7 @@ Bool VG_(saneUInstr) ( Bool beforeRA, Bool beforeLiveness, UInstr* u )
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case SSE3a_MemWr: return LIT0 && SZ416 && CC0 && Ls1 && Ls2 && TR3 && XOTHER;
|
||||
case SSE3a_MemRd: return LIT0 && SZ416 && CC0 && Ls1 && Ls2 && TR3 && XOTHER;
|
||||
case SSE3g_RegRd: return LIT0 && SZ4 && CC0 && Ls1 && Ls2 && TR3 && XOTHER;
|
||||
case SSE3: return LIT0 && SZ0 && CC0 && Ls1 && Ls2 && N3 && XOTHER;
|
||||
case SSE4: return LIT0 && SZ0 && CC0 && Ls1 && Ls2 && N3 && XOTHER;
|
||||
default:
|
||||
if (VG_(needs).extended_UCode)
|
||||
@ -876,6 +877,7 @@ Char* VG_(name_UOpcode) ( Bool upper, Opcode opc )
|
||||
case SSE2a_MemWr: return "SSE2a_MWr";
|
||||
case SSE2a_MemRd: return "SSE2a_MRd";
|
||||
case SSE3g_RegRd: return "SSE3g_RRd";
|
||||
case SSE3: return "SSE3";
|
||||
case SSE4: return "SSE4";
|
||||
case SSE3a_MemWr: return "SSE3a_MWr";
|
||||
case SSE3a_MemRd: return "SSE3a_MRd";
|
||||
@ -1051,6 +1053,12 @@ void pp_UInstrWorker ( Int instrNo, UInstr* u, Bool ppRegsLiveness )
|
||||
VG_(pp_UOperand)(u, 3, 4, True);
|
||||
break;
|
||||
|
||||
case SSE3:
|
||||
VG_(printf)("0x%x:0x%x:0x%x",
|
||||
(u->val1 >> 8) & 0xFF, u->val1 & 0xFF,
|
||||
u->val2 & 0xFF );
|
||||
break;
|
||||
|
||||
case SSE4:
|
||||
VG_(printf)("0x%x:0x%x:0x%x:0x%x",
|
||||
(u->val1 >> 8) & 0xFF, u->val1 & 0xFF,
|
||||
@ -1211,7 +1219,7 @@ Int VG_(get_reg_usage) ( UInstr* u, Tag tag, Int* regs, Bool* isWrites )
|
||||
case MMX2_RegRd: RD(2); break;
|
||||
case MMX2_RegWr: WR(2); break;
|
||||
|
||||
case SSE4:
|
||||
case SSE4: case SSE3:
|
||||
case MMX1: case MMX2: case MMX3:
|
||||
case NOP: case FPU: case INCEIP: case CALLM_S: case CALLM_E:
|
||||
case CLEAR: case CALLM: case LOCK: break;
|
||||
@ -1366,7 +1374,7 @@ Int maybe_uinstrReadsArchReg ( UInstr* u )
|
||||
case SSE2a_MemWr: case SSE2a_MemRd:
|
||||
case SSE3a_MemWr: case SSE3a_MemRd:
|
||||
case SSE3g_RegRd:
|
||||
case SSE4:
|
||||
case SSE4: case SSE3:
|
||||
case WIDEN:
|
||||
/* GETSEG and USESEG are to do with ArchRegS, not ArchReg */
|
||||
case GETSEG: case PUTSEG:
|
||||
@ -2233,11 +2241,22 @@ void VG_(translate) ( /*IN*/ ThreadState* tst,
|
||||
Bool debugging_translation;
|
||||
UChar* final_code;
|
||||
UCodeBlock* cb;
|
||||
Bool notrace_until_done;
|
||||
Int notrace_until_limit = 0;
|
||||
|
||||
VGP_PUSHCC(VgpTranslate);
|
||||
debugging_translation
|
||||
= orig_size == NULL || trans_addr == NULL || trans_size == NULL;
|
||||
|
||||
/* If codegen tracing, don't start tracing until
|
||||
notrace_until_limit blocks have gone by. This avoids printing
|
||||
huge amounts of useless junk when all we want to see is the last
|
||||
few blocks translated prior to a failure. Set
|
||||
notrace_until_limit to be the number of translations to be made
|
||||
before --trace-codegen= style printing takes effect. */
|
||||
notrace_until_done
|
||||
= VG_(overall_in_count) > notrace_until_limit;
|
||||
|
||||
if (!debugging_translation)
|
||||
VG_TRACK( pre_mem_read, Vg_CoreTranslate, tst, "", orig_addr, 1 );
|
||||
|
||||
@ -2245,7 +2264,7 @@ void VG_(translate) ( /*IN*/ ThreadState* tst,
|
||||
cb->orig_eip = orig_addr;
|
||||
|
||||
/* If doing any code printing, print a basic block start marker */
|
||||
if (VG_(clo_trace_codegen)) {
|
||||
if (VG_(clo_trace_codegen) && notrace_until_done) {
|
||||
Char fnname[64] = "";
|
||||
VG_(get_fnname_if_entry)(orig_addr, fnname, 64);
|
||||
VG_(printf)(
|
||||
@ -2256,8 +2275,10 @@ void VG_(translate) ( /*IN*/ ThreadState* tst,
|
||||
}
|
||||
|
||||
/* True if a debug trans., or if bit N set in VG_(clo_trace_codegen). */
|
||||
# define DECIDE_IF_PRINTING_CODEGEN_FOR_PHASE(n) \
|
||||
( debugging_translation || (VG_(clo_trace_codegen) & (1 << (n-1))) )
|
||||
# define DECIDE_IF_PRINTING_CODEGEN_FOR_PHASE(n) \
|
||||
( debugging_translation \
|
||||
|| (notrace_until_done \
|
||||
&& (VG_(clo_trace_codegen) & (1 << (n-1))) ))
|
||||
|
||||
/* Disassemble this basic block into cb. */
|
||||
VG_(print_codegen) = DECIDE_IF_PRINTING_CODEGEN_FOR_PHASE(1);
|
||||
|
||||
Loading…
x
Reference in New Issue
Block a user